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authorSubrata Banik <subrata.banik@intel.com>2019-07-05 16:00:38 +0530
committerSubrata Banik <subrata.banik@intel.com>2019-07-09 10:52:19 +0000
commitdf29d23ee3f36d3d6a5fa0fde46beeb67554a8da (patch)
tree93719f2cbd5fc31cbe613ba67fc703d66899e81a /src/soc/intel/icelake/romstage/romstage.c
parent45564050ec00b6d4b2c5b27cf26a56b46db8df1c (diff)
soc/intel/icelake: Refer to soc/soc_chip.h rather than chip.h
Change-Id: I9e3b5126173e7cec8f2809a38b92c82c9ed5327d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34085 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/icelake/romstage/romstage.c')
-rw-r--r--src/soc/intel/icelake/romstage/romstage.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c
index 514e5e8925..65e65cc80e 100644
--- a/src/soc/intel/icelake/romstage/romstage.c
+++ b/src/soc/intel/icelake/romstage/romstage.c
@@ -27,11 +27,10 @@
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <soc/romstage.h>
+#include <soc/soc_chip.h>
#include <string.h>
#include <timestamp.h>
-#include "../chip.h"
-
#define FSP_SMBIOS_MEMORY_INFO_GUID \
{ \
0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \