diff options
author | Aamir Bohra <aamir.bohra@intel.com> | 2018-10-17 11:55:01 +0530 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-26 11:20:54 +0000 |
commit | 3ee54bbf9413b5e174e65eff14769bdd2f5a3203 (patch) | |
tree | 1c27e4e0434d3e22e4fb9bb38ba59aa623070f80 /src/soc/intel/icelake/acpi/pci_irqs.asl | |
parent | bb7f4c7a4f3a076ba3e52fea9228e4a064316128 (diff) |
soc/intel/icelake: Do initial SoC commit
Clone entirely from Cannonlake
commit id: 3487095304dbbbf66de86f8bce0e40b7acb3ea27
List of changes on top off initial cannonlake clone
1. Replace "Cannonlake" with "Icelake"
2. Replace "cnl" with "icl"
3. Replace "cnp" with "icp"
4. Rename structrue based on Cannonlake with Icelake
5. Remove and clean below files
5.a. All NHLT blobs and related files.
5.b. remove cnl_memcfg_init.c file, will be added later.
5.c. Remove vr_config.c, this is WIP.
5.d. Clean up upd override in fsp_params.c,
will be added once FSP available.
5.e Remove CNL-H based GPIO configuartion.
Ice Lake specific changes will follow in subsequent patches.
Change-Id: I756fa7275c4190aebc0695f14484498aaf5662a5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/29162
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/icelake/acpi/pci_irqs.asl')
-rw-r--r-- | src/soc/intel/icelake/acpi/pci_irqs.asl | 141 |
1 files changed, 141 insertions, 0 deletions
diff --git a/src/soc/intel/icelake/acpi/pci_irqs.asl b/src/soc/intel/icelake/acpi/pci_irqs.asl new file mode 100644 index 0000000000..d346ce2269 --- /dev/null +++ b/src/soc/intel/icelake/acpi/pci_irqs.asl @@ -0,0 +1,141 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017-2018 Intel Corp. + * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/irq.h> + +Name (PICP, Package () { + /* PCI Bridge */ + /* cAVS, SMBus, GbE, Nothpeak */ + Package(){0x001FFFFF, 0, 0, cAVS_INTA_IRQ }, + Package(){0x001FFFFF, 1, 0, SMBUS_INTB_IRQ }, + Package(){0x001FFFFF, 2, 0, GbE_INTC_IRQ }, + Package(){0x001FFFFF, 3, 0, TRACE_HUB_INTD_IRQ }, + /* SerialIo and SCS */ + Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, + Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, + Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ }, + Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ }, + /* PCI Express Port 9-16 */ + Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ }, + Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ }, + Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ }, + Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ }, + /* PCI Express Port 1-8 */ + Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ }, + Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ }, + Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ }, + Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ }, + /* eMMC */ + Package(){0x001AFFFF, 0, 0, eMMC_IRQ }, + /* SerialIo */ + Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ }, + Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, + Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ }, + /* SATA controller */ + Package(){0x0017FFFF, 0, 0, SATA_IRQ }, + /* CSME (HECI, IDE-R, Keyboard and Text redirection */ + Package(){0x0016FFFF, 0, 0, HECI_1_IRQ }, + Package(){0x0016FFFF, 1, 0, HECI_2_IRQ }, + Package(){0x0016FFFF, 2, 0, IDER_IRQ }, + Package(){0x0016FFFF, 3, 0, KT_IRQ }, + /* SerialIo */ + Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ }, + Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, + Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, + Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, + /* D20: xHCI, OTG, SRAM, CNVi WiFi */ + Package(){0x0014FFFF, 0, 0, XHCI_IRQ }, + Package(){0x0014FFFF, 1, 0, OTG_IRQ }, + Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ }, + Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ }, + /* Integrated Sensor Hub */ + Package(){0x0013FFFF, 0, 0, ISH_IRQ }, + /* Thermal */ + Package(){0x0012FFFF, 0, 0, THERMAL_IRQ }, + /* Host Bridge */ + /* Root Port D1F0 */ + Package(){0x0001FFFF, 0, 0, PEG_RP_INTA_IRQ }, + Package(){0x0001FFFF, 1, 0, PEG_RP_INTB_IRQ }, + Package(){0x0001FFFF, 2, 0, PEG_RP_INTC_IRQ }, + Package(){0x0001FFFF, 3, 0, PEG_RP_INTD_IRQ }, + /* SA IGFX Device */ + Package(){0x0002FFFF, 0, 0, IGFX_IRQ }, + /* SA Thermal Device */ + Package(){0x0004FFFF, 0, 0, SA_THERMAL_IRQ }, + /* SA IPU Device */ + Package(){0x0005FFFF, 0, 0, IPU_IRQ }, + /* SA GNA Device */ + Package(){0x0008FFFF, 0, 0, GNA_IRQ }, +}) + +Name (PICN, Package () { + /* D31: cAVS, SMBus, GbE, Nothpeak */ + Package () { 0x001FFFFF, 0, \_SB.PCI0.LNKA, 0 }, + Package () { 0x001FFFFF, 1, \_SB.PCI0.LNKB, 0 }, + Package () { 0x001FFFFF, 2, \_SB.PCI0.LNKC, 0 }, + Package () { 0x001FFFFF, 3, \_SB.PCI0.LNKD, 0 }, + /* D32: Can't use PIC*/ + /* D29: PCI Express Port 9-16 */ + Package () { 0x001DFFFF, 0, \_SB.PCI0.LNKA, 0 }, + Package () { 0x001DFFFF, 1, \_SB.PCI0.LNKB, 0 }, + Package () { 0x001DFFFF, 2, \_SB.PCI0.LNKC, 0 }, + Package () { 0x001DFFFF, 3, \_SB.PCI0.LNKD, 0 }, + /* D28: PCI Express Port 1-8 */ + Package () { 0x001CFFFF, 0, \_SB.PCI0.LNKA, 0 }, + Package () { 0x001CFFFF, 1, \_SB.PCI0.LNKB, 0 }, + Package () { 0x001CFFFF, 2, \_SB.PCI0.LNKC, 0 }, + Package () { 0x001CFFFF, 3, \_SB.PCI0.LNKD, 0 }, + /* D25: Can't use PIC*/ + /* D23 */ + Package () { 0x0017FFFF, 0, \_SB.PCI0.LNKA, 0 }, + /* D22: CSME (HECI, IDE-R, KT redirection */ + Package () { 0x0016FFFF, 0, \_SB.PCI0.LNKA, 0 }, + Package () { 0x0016FFFF, 1, \_SB.PCI0.LNKB, 0 }, + Package () { 0x0016FFFF, 2, \_SB.PCI0.LNKC, 0 }, + Package () { 0x0016FFFF, 3, \_SB.PCI0.LNKD, 0 }, + /* D21: Can't use PIC*/ + /* D20: xHCI, OTG, SRAM, CNVi WiFi */ + Package () { 0x0014FFFF, 0, \_SB.PCI0.LNKA, 0 }, + Package () { 0x0014FFFF, 1, \_SB.PCI0.LNKB, 0 }, + Package () { 0x0014FFFF, 2, \_SB.PCI0.LNKC, 0 }, + Package () { 0x0014FFFF, 3, \_SB.PCI0.LNKD, 0 }, + /* D19: Can't use PIC*/ + /* Thermal */ + Package () { 0x0012FFFF, 0, \_SB.PCI0.LNKA, 0 }, + /* P.E.G. Root Port D1F0 */ + Package () { 0x0001FFFF, 0, \_SB.PCI0.LNKA, 0 }, + Package () { 0x0001FFFF, 1, \_SB.PCI0.LNKB, 0 }, + Package () { 0x0001FFFF, 2, \_SB.PCI0.LNKC, 0 }, + Package () { 0x0001FFFF, 3, \_SB.PCI0.LNKD, 0 }, + /* SA IGFX Device */ + Package () { 0x0002FFFF, 0, \_SB.PCI0.LNKA, 0 }, + /* SA Thermal Device */ + Package () { 0x0004FFFF, 0, \_SB.PCI0.LNKA, 0 }, + /* SA IPU Device */ + Package () { 0x0005FFFF, 0, \_SB.PCI0.LNKA, 0 }, + /* SA GNA Device */ + Package () { 0x0008FFFF, 0, \_SB.PCI0.LNKA, 0 }, +}) + +Method (_PRT) +{ + If (PICM) { + Return (^PICP) + } Else { + Return (^PICN) + } +} |