soc/intel/icelake: Add chipset event logging

This patch ports CB:30718 and CB:31908 changes from CNL to ICL.

Add logging of chipset events on boot into the flash event log.
This was tested on a google/dragonegg board to ensure that events
like "System Reset" are added to the log as expected.

Also fix GEN_PMCON bit checks as below:
ICL PCH has PWR_FLR, SUS_PWR_FLR and HOST_RST_STS bits in GEN_PMCON_A
and so this change updates the check for these bits to use GEN_PMCON_A
instead of GEN_PMCON_B.

Change-Id: I25ec32e81f8801f8d5e69c6095ffed73d75dded6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc
index 74c9182067..cd6a6ba842 100644
--- a/src/soc/intel/icelake/Makefile.inc
+++ b/src/soc/intel/icelake/Makefile.inc
@@ -35,6 +35,7 @@ romstage-y += uart.c
 ramstage-y += acpi.c
 ramstage-y += chip.c
 ramstage-y += cpu.c
+ramstage-y += elog.c
 ramstage-y += finalize.c
 ramstage-y += fsp_params.c
 ramstage-y += gpio.c