From 5489341e6380cb8c7d1249a495486ae9cfcd4fa2 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 29 Apr 2019 13:28:11 +0530 Subject: soc/intel/icelake: Add chipset event logging This patch ports CB:30718 and CB:31908 changes from CNL to ICL. Add logging of chipset events on boot into the flash event log. This was tested on a google/dragonegg board to ensure that events like "System Reset" are added to the log as expected. Also fix GEN_PMCON bit checks as below: ICL PCH has PWR_FLR, SUS_PWR_FLR and HOST_RST_STS bits in GEN_PMCON_A and so this change updates the check for these bits to use GEN_PMCON_A instead of GEN_PMCON_B. Change-Id: I25ec32e81f8801f8d5e69c6095ffed73d75dded6 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/32504 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Rizwan Qureshi --- src/soc/intel/icelake/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/icelake/Makefile.inc') diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index 74c9182067..cd6a6ba842 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -35,6 +35,7 @@ romstage-y += uart.c ramstage-y += acpi.c ramstage-y += chip.c ramstage-y += cpu.c +ramstage-y += elog.c ramstage-y += finalize.c ramstage-y += fsp_params.c ramstage-y += gpio.c -- cgit v1.2.3