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authorMichael Niewöhner <foss@mniewoehner.de>2021-01-01 21:26:42 +0100
committerMichael Niewöhner <foss@mniewoehner.de>2021-01-11 20:49:53 +0000
commit8a6c34e8ba9862814e53ad4f9b04ae1f2b9d4b49 (patch)
treeb4edf89d40b02f27ba4da19d04fa2217e2d5a1de /src/soc/intel/icelake/Kconfig
parent11fae4ffe019ad648e517115aa1ec7bedbf4f648 (diff)
soc/intel/{icl,tgl,jsl,ehl}: add LPIT support
Add SLP_S0 residency register and enable LPIT support. Change-Id: Id1abbe8dcb7796eeb26ccb72f1f26cf7a040dba4 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49048 Reviewed-by: Lance Zhao Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/icelake/Kconfig')
-rw-r--r--src/soc/intel/icelake/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig
index 06c1a9b83e..d1efa5570e 100644
--- a/src/soc/intel/icelake/Kconfig
+++ b/src/soc/intel/icelake/Kconfig
@@ -42,6 +42,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_ACPI
+ select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
select SOC_INTEL_COMMON_BLOCK_CAR
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
select SOC_INTEL_COMMON_BLOCK_CNVI