From 8a6c34e8ba9862814e53ad4f9b04ae1f2b9d4b49 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Fri, 1 Jan 2021 21:26:42 +0100 Subject: soc/intel/{icl,tgl,jsl,ehl}: add LPIT support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add SLP_S0 residency register and enable LPIT support. Change-Id: Id1abbe8dcb7796eeb26ccb72f1f26cf7a040dba4 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/49048 Reviewed-by: Lance Zhao Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/soc/intel/icelake/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/icelake/Kconfig') diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 06c1a9b83e..d1efa5570e 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -42,6 +42,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI -- cgit v1.2.3