diff options
author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/soc/intel/fsp_broadwell_de | |
parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/fsp_broadwell_de')
-rw-r--r-- | src/soc/intel/fsp_broadwell_de/chip.c | 4 | ||||
-rw-r--r-- | src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c | 34 | ||||
-rw-r--r-- | src/soc/intel/fsp_broadwell_de/romstage/romstage.c | 4 | ||||
-rw-r--r-- | src/soc/intel/fsp_broadwell_de/southcluster.c | 6 |
4 files changed, 24 insertions, 24 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/chip.c b/src/soc/intel/fsp_broadwell_de/chip.c index f6dd2a7021..348e1c00f1 100644 --- a/src/soc/intel/fsp_broadwell_de/chip.c +++ b/src/soc/intel/fsp_broadwell_de/chip.c @@ -30,7 +30,7 @@ static void pci_domain_set_resources(struct device *dev) assign_resources(dev->link_list); } -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) static const char *domain_acpi_name(const struct device *dev) { if (dev->path.type == DEVICE_PATH_DOMAIN) @@ -45,7 +45,7 @@ static struct device_operations pci_domain_ops = { .enable_resources = NULL, .init = NULL, .scan_bus = pci_domain_scan_bus, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_name = domain_acpi_name #endif }; diff --git a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c index b8ef6b18b4..54e796d48d 100644 --- a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c @@ -51,22 +51,22 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) /* * Serial Port */ - if (IS_ENABLED(CONFIG_INTEGRATED_UART)) { + if (CONFIG(INTEGRATED_UART)) { UpdData->SerialPortConfigure = 1; /* values are from FSP .bsf file */ - if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_9600)) + if (CONFIG(CONSOLE_SERIAL_9600)) UpdData->SerialPortBaudRate = 8; - else if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_19200)) + else if (CONFIG(CONSOLE_SERIAL_19200)) UpdData->SerialPortBaudRate = 9; - else if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_38400)) + else if (CONFIG(CONSOLE_SERIAL_38400)) UpdData->SerialPortBaudRate = 10; - else if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_57600)) + else if (CONFIG(CONSOLE_SERIAL_57600)) UpdData->SerialPortBaudRate = 11; - else if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_115200)) + else if (CONFIG(CONSOLE_SERIAL_115200)) UpdData->SerialPortBaudRate = 12; } - if (!IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + if (!CONFIG(CONSOLE_SERIAL)) UpdData->SerialPortType = 0; UpdData->DebugOutputLevel = CONFIG_FSP_DEBUG_LEVEL; @@ -74,19 +74,19 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) /* * Memory Down */ - if (IS_ENABLED(CONFIG_FSP_MEMORY_DOWN)) { + if (CONFIG(FSP_MEMORY_DOWN)) { UpdData->MemDownEnable = 1; - if (IS_ENABLED(CONFIG_FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT)) + if (CONFIG(FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT)) UpdData->MemDownCh0Dimm0SpdPtr = (UINT32)cbfs_boot_map_with_leak("spd_ch0_dimm0.bin", CBFS_TYPE_SPD, NULL); - if (IS_ENABLED(CONFIG_FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT)) + if (CONFIG(FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT)) UpdData->MemDownCh0Dimm1SpdPtr = (UINT32)cbfs_boot_map_with_leak("spd_ch0_dimm1.bin", CBFS_TYPE_SPD, NULL); - if (IS_ENABLED(CONFIG_FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT)) + if (CONFIG(FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT)) UpdData->MemDownCh1Dimm0SpdPtr = (UINT32)cbfs_boot_map_with_leak("spd_ch1_dimm0.bin", CBFS_TYPE_SPD, NULL); - if (IS_ENABLED(CONFIG_FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT)) + if (CONFIG(FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT)) UpdData->MemDownCh1Dimm1SpdPtr = (UINT32)cbfs_boot_map_with_leak("spd_ch1_dimm1.bin", CBFS_TYPE_SPD, NULL); } else { @@ -98,7 +98,7 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) /* * Fast Boot */ - if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) + if (CONFIG(ENABLE_MRC_CACHE)) UpdData->MemFastBoot = 1; else UpdData->MemFastBoot = 0; @@ -106,18 +106,18 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) /* * Hyper-Threading */ - if (IS_ENABLED(CONFIG_FSP_HYPERTHREADING)) + if (CONFIG(FSP_HYPERTHREADING)) UpdData->HyperThreading = 1; else UpdData->HyperThreading = 0; /* Enable USB */ - if (IS_ENABLED(CONFIG_FSP_EHCI1_ENABLE)) + if (CONFIG(FSP_EHCI1_ENABLE)) UpdData->Ehci1Enable = 1; else UpdData->Ehci1Enable = 0; - if (IS_ENABLED(CONFIG_FSP_EHCI2_ENABLE)) + if (CONFIG(FSP_EHCI2_ENABLE)) UpdData->Ehci2Enable = 1; else UpdData->Ehci2Enable = 0; @@ -133,7 +133,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, FSP_INFO_HEADER *fs ConfigureDefaultUpdData(pFspRtBuffer->Common.UpdDataRgnPtr); pFspInitParams->NvsBufferPtr = NULL; -#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) +#if CONFIG(ENABLE_MRC_CACHE) /* Find the fastboot cache that was saved in the ROM */ pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); #endif diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index 80795c303e..32429ae236 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -61,7 +61,7 @@ static void setup_gpio_io_address(void) void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header) { post_code(0x40); - if (!IS_ENABLED(CONFIG_INTEGRATED_UART)) { + if (!CONFIG(INTEGRATED_UART)) { /* Enable decoding of I/O locations for Super I/O devices */ pci_write_config16(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), LPC_IO_DEC, 0x0010); @@ -105,7 +105,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) __func__, (u32) status, (u32) hob_list_ptr); /* FSP reconfigures USB, so reinit it to have debug */ - if (IS_ENABLED(CONFIG_USBDEBUG_IN_PRE_RAM)) + if (CONFIG(USBDEBUG_IN_PRE_RAM)) usbdebug_hw_init(true); printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status); diff --git a/src/soc/intel/fsp_broadwell_de/southcluster.c b/src/soc/intel/fsp_broadwell_de/southcluster.c index 5c0cb7e5ab..5b90bbbdd1 100644 --- a/src/soc/intel/fsp_broadwell_de/southcluster.c +++ b/src/soc/intel/fsp_broadwell_de/southcluster.c @@ -228,7 +228,7 @@ static void sc_init(struct device *dev) /* Program Serial IRQ register. */ pci_write_config8(dev, SIRQ_CNTL, SIRQ_EN | SIRQ_MODE_CONT); - if (!IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)) { + if (!CONFIG(SERIRQ_CONTINUOUS_MODE)) { /* If SERIRQ have to operate in quiet mode, it should have been run in continuous mode for at least one frame first. Use I/O access to achieve the delay of at least one LPC cycle. */ @@ -263,7 +263,7 @@ void southcluster_enable_dev(struct device *dev) } } -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) static const char *lpc_acpi_name(const struct device *dev) { if (dev->path.pci.devfn == LPC_DEV_FUNC) @@ -281,7 +281,7 @@ static struct device_operations device_ops = { .enable = southcluster_enable_dev, .scan_bus = scan_lpc_bus, .ops_pci = &soc_pci_ops, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_name = lpc_acpi_name, #endif }; |