diff options
| author | Keith Short <keithshort@chromium.org> | 2019-05-16 14:07:43 -0600 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2019-05-22 16:53:19 +0000 |
| commit | bb41aba0d8c3c3cbfee44b0f7267e78fb7d012ee (patch) | |
| tree | 66c4acc7abb2d19c37dbe8d470a87d64a0637631 /src/soc/intel/fsp_broadwell_de | |
| parent | 1835bf0fd4b77ab3eae1fb085be1667d13ed3144 (diff) | |
post_code: add post code for invalid vendor binary
Add a new post code POST_INVALID_VENDOR_BINARY, used when coreboot fails
to locate or validate a vendor supplied binary.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
Change-Id: Ib1e359d4e8772c37922b1b779135e58c73bff6b4
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/soc/intel/fsp_broadwell_de')
| -rw-r--r-- | src/soc/intel/fsp_broadwell_de/romstage/romstage.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index a75dabd225..121cb25d61 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -84,7 +84,8 @@ void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header) post_code(0x48); printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n"); fsp_early_init(fsp_info_header); - die("Uh Oh! fsp_early_init should not return here.\n"); + die_with_post_code(POST_INVALID_VENDOR_BINARY, + "Uh Oh! fsp_early_init should not return here.\n"); } /******************************************************************************* |