soc/intel/fsp_broadwell_de: Enable early integrated UART

In order to use internal UART it needs to 'enabled'. This is normally done
by FSP. However sometimes internal UART is needed before FSP is invoked.

TEST=check if printk() show up in early romstage. Tested on OCP Monolake.
Tested on out-of-tree mainboard to see if UART on LPC still works.

Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I88a7b1a38abf9a09137f6dd75a5a9dee104daaca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34683
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 45 insertions, 0 deletions

diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
index 38cd9476c5..085395e9a8 100644
--- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
+++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
@@ -32,6 +32,8 @@
 #include <soc/pci_devs.h>
 #include <soc/romstage.h>
 #include <soc/gpio.h>
+#include <soc/vtd.h>
+#include <soc/ubox.h>
 #include <build.h>
 
 static void init_rtc(void)
@@ -55,6 +57,47 @@ static void setup_gpio_io_address(void)
 }
 
 
+static void enable_integrated_uart(uint8_t port)
+{
+	uint32_t reg32, busno1 = 0, ubox_uart_en = 0, dfx1 = 0;
+	pci_devfn_t vtd_dev, ubox_dev;
+
+	vtd_dev = PCI_DEV(BUS0, VTD_DEV, VTD_FUNC);
+
+	/* Figure out what bus number is assigned for CPUBUSNO(1) */
+	reg32 = pci_mmio_read_config32(vtd_dev, VTD_CPUBUSNO);
+	busno1 = (reg32 >> VTD_CPUBUSNO_BUS1_SHIFT) & VTD_CPUBUSNO_BUS1_MASK;
+
+	/* UBOX sits on CPUBUSNO(1) */
+	ubox_dev = PCI_DEV(busno1, UBOX_DEV, UBOX_FUNC);
+	uint32_t reset_sts = pci_mmio_read_config32(ubox_dev, UBOX_SC_RESET_STATUS);
+
+	/* In case we are in bypass mode do nothing */
+	if (reset_sts & UBOX_SC_BYPASS)
+		return;
+
+	dfx1 = pci_mmio_read_config32(vtd_dev, VTD_DFX1);
+	ubox_uart_en = pci_mmio_read_config32(ubox_dev, UBOX_UART_ENABLE);
+
+	switch (port) {
+	case 0:
+		ubox_uart_en |= UBOX_UART_ENABLE_PORT0;
+		dfx1 |= VTD_DFX1_RANGE_3F8_DISABLE;
+		break;
+	case 1:
+		ubox_uart_en |= UBOX_UART_ENABLE_PORT1;
+		dfx1 |= VTD_DFX1_RANGE_2F8_DISABLE;
+		break;
+	default:
+		printk(BIOS_ERR, "incorrect port number\n");
+		return;
+	}
+
+	/* Disable decoding and enable the port we want */
+	pci_mmio_write_config32(vtd_dev, VTD_DFX1, dfx1);
+	pci_mmio_write_config32(ubox_dev, UBOX_UART_ENABLE, ubox_uart_en);
+}
+
 /* Entry from cache-as-ram.inc. */
 void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header)
 {
@@ -65,6 +108,8 @@ void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header)
 					   LPC_IO_DEC, 0x0010);
 		pci_write_config16(PCI_DEV(0x0, LPC_DEV, LPC_FUNC),
 					   LPC_EN, 0x340f);
+	} else {
+		enable_integrated_uart(CONFIG_UART_FOR_CONSOLE);
 	}
 
 	/* Call into mainboard. */