fsp_broadwell_de: Add SMM code

Add basic SMM support for Broadwell-DE SoC.

The code is mainly based on the SMM implementation of Broadwell with a
few differences:
- EMRR is now called PRMRR and the UNCORE part of it is not available
- SMM_FEATURE_CONTROL is no longer a MSR but is now located in PCI space
- currently only SERIRQ-SMI has a handler

Change-Id: I461a14d411aedefdb0cb54ae43b91103a80a4f6a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/19145
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

5 files changed, 143 insertions, 7 deletions

diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h b/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h
index 85298a5ccd..4c11f386dd 100644
--- a/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2013 Google, Inc.
  * Copyright (C) 2015-2016 Intel Corp.
+ * Copyright (C) 2017 Siemens AG
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -20,4 +21,9 @@
 #define VTBAR_OFFSET		0x180
 #define VTBAR_MASK		0xffffe000
 
+#define SMM_FEATURE_CONTROL	0x58
+#define  SMM_CPU_SAVE_EN	(1 << 1)
+#define TSEG_BASE		0xa8	/* TSEG base */
+#define TSEG_LIMIT		0xac	/* TSEG limit */
+
 #endif /* _SOC_BROADWELL_DE_H_ */
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h b/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h
index 8cf8889c3f..6a91f8fd2d 100644
--- a/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2013 Google Inc.
  * Copyright (C) 2015-2016 Intel Corp.
+ * Copyright (C) 2017 Siemens AG
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -34,6 +35,9 @@
 #define LPC_GEN3_DEC		0x8c
 #define LPC_GEN4_DEC		0x90
 #define GEN_PMCON_1		0xA0
+#define   SMI_LOCK		(1 << 4)
+#define   SMI_LOCK_GP6		(1 << 5)
+#define   SMI_LOCK_GP22		(1 << 6)
 #define GEN_PMCON_2		0xA2
 #define GEN_PMCON_3		0xA4
 #define   RTC_PWR_STS		(1 << 2)
@@ -72,6 +76,22 @@
 #define   HOT_PLUG_STS		(1 << 1)
 #define GPE0_EN			0x28
 #define SMI_EN			0x30
+#define  XHCI_SMI_EN		(1 << 31)
+#define  ME_SMI_EN		(1 << 30)
+#define  GPIO_UNLOCK_SMI_EN	(1 << 27)
+#define  INTEL_USB2_EN		(1 << 18)
+#define  LEGACY_USB2_EN		(1 << 17)
+#define  PERIODIC_EN		(1 << 14)
+#define  TCO_EN			(1 << 13)
+#define  MCSMI_EN		(1 << 11)
+#define  BIOS_RLS		(1 <<  7)
+#define  SWSMI_TMR_EN		(1 <<  6)
+#define  APMC_EN		(1 <<  5)
+#define  SLP_SMI_EN		(1 <<  4)
+#define  LEGACY_USB_EN		(1 <<  3)
+#define  BIOS_EN		(1 <<  2)
+#define  EOS			(1 <<  1)
+#define  GBL_SMI_EN		(1 <<  0)
 #define SMI_STS			0x34
 #define ALT_GPIO_SMI		0x38
 #define UPRWC			0x3c
@@ -87,4 +107,17 @@
 #define   TCO_TMR_HALT		(1 << 11)
 #define TCO_TMR			0x70
 
+/* PM1_CNT */
+void enable_pm1_control(uint32_t mask);
+void disable_pm1_control(uint32_t mask);
+
+/* PM1 */
+uint16_t clear_pm1_status(void);
+void enable_pm1(uint16_t events);
+uint32_t clear_smi_status(void);
+
+/* SMI */
+void enable_smi(uint32_t mask);
+void disable_smi(uint32_t mask);
+
 #endif /* _SOC_LPC_H_ */
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h
index da9ebb9921..f5ea34ccd3 100644
--- a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2013 Google, Inc.
  * Copyright (C) 2015-2016 Intel Corp.
+ * Copyright (C) 2017 Siemens AG
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -17,12 +18,25 @@
 #ifndef _SOC_MSR_H_
 #define _SOC_MSR_H_
 
-#define MSR_IA32_PLATFORM_ID    0x17
-#define MSR_CORE_THREAD_COUNT   0x35
-#define MSR_PLATFORM_INFO       0xce
-#define MSR_TURBO_RATIO_LIMIT   0x1ad
-#define MSR_IA32_MC0_STATUS     0x400
-#define MSR_PKG_POWER_SKU_UNIT  0x606
-#define MSR_PKG_POWER_LIMIT     0x610
+#define MSR_IA32_PLATFORM_ID	0x17
+#define MSR_CORE_THREAD_COUNT	0x35
+#define MSR_PLATFORM_INFO	0xce
+#define MSR_TURBO_RATIO_LIMIT	0x1ad
+#define MSR_IA32_MC0_STATUS	0x400
+#define MSR_PKG_POWER_SKU_UNIT	0x606
+#define MSR_PKG_POWER_LIMIT	0x610
+
+#define SMM_MCA_CAP_MSR		0x17d
+#define  SMM_CPU_SVRSTR_BIT	57
+#define  SMM_CPU_SVRSTR_MASK	(1 << (SMM_CPU_SVRSTR_BIT - 32))
+
+/* SMM save state MSRs */
+#define SMBASE_MSR		0xc20
+#define IEDBASE_MSR		0xc22
+/* MTRR_CAP_MSR bits */
+#define SMRR_SUPPORTED		(1 << 11)
+#define PRMRR_SUPPORTED		(1 << 12)
+#define PRMRRphysBase_MSR	0x1f4
+#define PRMRRphysMask_MSR	0x1f5
 
 #endif /* _SOC_MSR_H_ */
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h b/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h
index c5bb77ab75..5fb8113980 100644
--- a/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2013 Google Inc.
  * Copyright (C) 2015-2016 Intel Corp.
+ * Copyright (C) 2017 Siemens AG
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -119,4 +120,10 @@
 #define PCIE_PORT7_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT7_FUNC)
 #define PCIE_PORT8_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT8_FUNC)
 
+/* The SMM device is located on bus 0xff (QPI) */
+#define QPI_BUS			0xff
+#define SMM_DEV			0x10
+#define SMM_FUNC		0x06
+#define SMM_DEV_FUNC		PCI_DEVFN(SMM_DEV, SMM_FUNC)
+
 #endif /* _SOC_PCI_DEVS_H_ */
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h
new file mode 100644
index 0000000000..ab8ca8eb71
--- /dev/null
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2017 Siemens AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _BROADWELL_SMM_H_
+#define _BROADWELL_SMM_H_
+
+#include <stdint.h>
+#include <cpu/x86/msr.h>
+
+struct ied_header {
+	char signature[10];
+	u32 size;
+	u8 reserved[34];
+} __attribute__ ((packed));
+
+struct smm_relocation_params {
+	u32 smram_base;
+	u32 smram_size;
+	u32 ied_base;
+	u32 ied_size;
+	msr_t smrr_base;
+	msr_t smrr_mask;
+	msr_t prmrr_base;
+	msr_t prmrr_mask;
+	/* The smm_save_state_in_msrs field indicates if SMM save state
+	   locations live in MSRs. This indicates to the CPUs how to adjust
+	   the SMMBASE and IEDBASE. */
+	int smm_save_state_in_msrs;
+};
+
+/*
+ * There is a bug in the order of Kconfig includes in that arch/x86/Kconfig
+ * is included after chipset code. This causes the chipset's Kconfig to be
+ * clobbered by the arch/x86/Kconfig if they have the same name.
+ */
+static inline int smm_region_size(void)
+{
+	/* Make it 8MiB by default. */
+	if (CONFIG_SMM_TSEG_SIZE == 0)
+		return (8 << 20);
+	return CONFIG_SMM_TSEG_SIZE;
+}
+
+void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
+				uintptr_t staggered_smbase);
+void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
+		size_t *smm_save_state_size);
+void smm_initialize(void);
+void smm_relocate(void);
+
+/* These helpers are for performing SMM relocation. */
+void southbridge_trigger_smi(void);
+void southbridge_clear_smi_status(void);
+
+/*
+ * The initialization of the southbridge is split into 2 components. One is
+ * for clearing the state in the SMM registers. The other is for enabling
+ * SMIs. They are split so that other work between the 2 actions.
+ */
+void southbridge_smm_clear_state(void);
+void southbridge_smm_enable_smi(void);
+
+#endif