diff options
| author | Duncan Laurie <dlaurie@google.com> | 2019-02-15 08:31:48 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-02-18 20:24:27 +0000 |
| commit | cd7873a28a311847bdd1fd7f74d2a6d0f66ede62 (patch) | |
| tree | 89312ec1f412e9733fa87b206a2a3ec4dc35c542 /src/soc/intel/fsp_broadwell_de/acpi | |
| parent | 2cb7de09b2a56b05a9c44846b62f70150c591043 (diff) | |
mb/google/sarien: Swap FMAP location for RW_LEGACY and NVRAM
The Intel SOC can only shadow the top 16MB of SPI into memory so
in order to make it easier to access the NVRAM region with memory
mapped interface move it above the much larger RW_LEGACY region.
I tested to confirm that this region can now be read via MMIO
interface and does not need to use the hwseq SPI controller.
Change-Id: Iafacb01eec07beaf474b6a1f2b36a77117e327da
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Diffstat (limited to 'src/soc/intel/fsp_broadwell_de/acpi')
0 files changed, 0 insertions, 0 deletions