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| author | Werner Zeh <werner.zeh@siemens.com> | 2017-04-06 10:01:24 +0200 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2017-04-28 06:19:20 +0200 |
| commit | 97c0979befedb822e9d77bc0e11374e291332c49 (patch) | |
| tree | bafd0c0ef23af3e1bf22da14cd47655ee5f5ed2e /src/soc/intel/fsp_broadwell_de/Kconfig | |
| parent | 00d250e2289de2e39ab6f69a61176405cdfa9ddb (diff) | |
fsp_broadwell_de: Add SMM code
Add basic SMM support for Broadwell-DE SoC.
The code is mainly based on the SMM implementation of Broadwell with a
few differences:
- EMRR is now called PRMRR and the UNCORE part of it is not available
- SMM_FEATURE_CONTROL is no longer a MSR but is now located in PCI space
- currently only SERIRQ-SMI has a handler
Change-Id: I461a14d411aedefdb0cb54ae43b91103a80a4f6a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/19145
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/fsp_broadwell_de/Kconfig')
| -rw-r--r-- | src/soc/intel/fsp_broadwell_de/Kconfig | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index 8442963977..cfe3fb05b8 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -23,6 +23,8 @@ config CPU_SPECIFIC_OPTIONS # Microcode header files are delivered in FSP package select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN select HAVE_INTEL_FIRMWARE + select SMM_TSEG + select HAVE_SMI_HANDLER config CBFS_SIZE hex @@ -56,6 +58,14 @@ config VGA_BIOS bool default n +config SMM_TSEG_SIZE + hex + default 0x800000 + +config SMM_RESERVED_SIZE + hex + default 0x100000 + config INTEGRATED_UART bool "Integrated UART ports" default y |