fsp_baytrail: Add the FSP version of Intel's Bay Trail-I chip

While similar to the Bay Trail-M/D code based on the MRC, there are
many differences as well:
- Obviously, uses the FSP instead of the MRC binaries.
- FSP does additional hardware setup, so coreboot doesn't need to.
- Different microcode & microcode loading method
- Uses the cache_as_ram.inc from the FSP Driver
- Various other changes in support of the FSP
Additional changes that don't have to to with the FSP vs MRC:
- Updated IRQ Routing
- Different FADT implementation.
This was validated with FSP:
BAYTRAIL_FSP_GOLD_002_10-JANUARY-2014.fd
SHA256: d29eefbb33454bd5314bfaa38fb055d592a757de7b348ed7096cd8c2d65908a5
MD5: 9360cd915f0d3e4116bbc782233d7b91

Change-Id: Iadadf8cd6cf444ba840e0f76d3aed7825cd7aee4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5791
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

5 files changed, 425 insertions, 0 deletions

diff --git a/src/soc/intel/fsp_baytrail/romstage/Makefile.inc b/src/soc/intel/fsp_baytrail/romstage/Makefile.inc
new file mode 100644
index 0000000000..ff7762eda7
--- /dev/null
+++ b/src/soc/intel/fsp_baytrail/romstage/Makefile.inc
@@ -0,0 +1,26 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2013 Google Inc.
+# Copyright (C) 2014 Sage Electronic Engineering, LLC.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+romstage-y += romstage.c
+romstage-y += pmc.c
+romstage-y += report_platform.c
+romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c
+
+$(obj)/soc/intel/fsp_baytrail/romstage/romstage.romstage.o : $(obj)/build.h
\ No newline at end of file
diff --git a/src/soc/intel/fsp_baytrail/romstage/pmc.c b/src/soc/intel/fsp_baytrail/romstage/pmc.c
new file mode 100644
index 0000000000..678f951fe5
--- /dev/null
+++ b/src/soc/intel/fsp_baytrail/romstage/pmc.c
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stddef.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <baytrail/iomap.h>
+#include <baytrail/iosf.h>
+#include <baytrail/lpc.h>
+#include <baytrail/pci_devs.h>
+#include <baytrail/pmc.h>
+#include <baytrail/romstage.h>
+#include "../chip.h"
+
+void tco_disable(void)
+{
+	uint32_t reg;
+
+	reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT);
+	reg |= TCO_TMR_HALT;
+	outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT);
+}
+
diff --git a/src/soc/intel/fsp_baytrail/romstage/report_platform.c b/src/soc/intel/fsp_baytrail/romstage/report_platform.c
new file mode 100644
index 0000000000..37e40ba07c
--- /dev/null
+++ b/src/soc/intel/fsp_baytrail/romstage/report_platform.c
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <baytrail/iosf.h>
+#include <baytrail/romstage.h>
+#include <cpu/x86/msr.h>
+#include <baytrail/msr.h>
+#include <cpu/x86/name.h>
+
+static void print_dram_info(void)
+{
+	const int mrc_ver_reg = 0xf0;
+	const uint32_t soc_dev = PCI_DEV(0, SOC_DEV, SOC_FUNC);
+	uint32_t reg;
+	int num_channels;
+	int speed;
+	uint32_t ch0;
+	uint32_t ch1;
+
+	reg = pci_read_config32(soc_dev, mrc_ver_reg);
+
+	printk(BIOS_INFO, "MRC v%d.%02d\n", (reg >> 8) & 0xff, reg & 0xff);
+
+	/* Number of channels enabled and DDR3 type. Determine number of
+	 * channels by the keying of the rank enable bits [3:0]. * */
+	ch0 = iosf_dunit_ch0_read(DRP);
+	ch1 = iosf_dunit_ch1_read(DRP);
+	num_channels = 0;
+	if (ch0 & DRP_RANK_MASK)
+		num_channels++;
+	if (ch1 & DRP_RANK_MASK)
+		num_channels++;
+
+	printk(BIOS_INFO, "%d channels of %sDDR3 @ ", num_channels,
+	       (reg & (1 << 22)) ? "LP" : "");
+
+	/* DRAM frequency -- all channels run at same frequency. */
+	reg = iosf_dunit_read(DTR0);
+	switch (reg & 0x3) {
+	case 0:
+		speed = 800; break;
+	case 1:
+		speed = 1066; break;
+	case 2:
+		speed = 1333; break;
+	case 3:
+		speed = 1600; break;
+	}
+	printk(BIOS_INFO, "%dMHz\n", speed);
+}
+
+#define VARIANT_ID_BYTE	18
+#define VARIANT_ID_MASK 7
+void report_platform_info(void)
+{
+	const char *baytrail_variants[4] = {
+		"Bay Trail-I (ISG/embedded)",
+		"Bay Trail-T (Tablet)",
+		"Bay Trail-D (Desktop)",
+		"Bay Trail-M (Mobile)",
+	};
+	msr_t platform_id = rdmsr(MSR_IA32_PLATFORM_ID);
+	uint8_t variant = (platform_id.hi >> VARIANT_ID_BYTE) & VARIANT_ID_MASK;
+
+	printk(BIOS_INFO, "Baytrail Chip Variant: %s\n", variant < 4 ?
+	       baytrail_variants[variant] : "Unknown");
+	print_dram_info();
+
+}
diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c
new file mode 100644
index 0000000000..a63156ff11
--- /dev/null
+++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c
@@ -0,0 +1,232 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stddef.h>
+#include <arch/cpu.h>
+#include <lib.h>
+#include <arch/io.h>
+#include <arch/cbfs.h>
+#include <arch/stages.h>
+#include <console/console.h>
+#include <cbmem.h>
+#include <cpu/x86/mtrr.h>
+#include <romstage_handoff.h>
+#include <timestamp.h>
+#include <baytrail/gpio.h>
+#include <baytrail/iomap.h>
+#include <baytrail/lpc.h>
+#include <baytrail/pci_devs.h>
+#include <baytrail/romstage.h>
+#include <baytrail/acpi.h>
+#include <baytrail/baytrail.h>
+#include <drivers/intel/fsp/fsp_util.h>
+#include <baytrail/pmc.h>
+#include <baytrail/spi.h>
+#include <build.h>
+#include <pc80/mc146818rtc.h>
+#include <device/pci_def.h>
+#include <console/cbmem_console.h>
+
+static void program_base_addresses(void)
+{
+	uint32_t reg;
+
+	/* Memory Mapped IO registers. */
+	reg = PMC_BASE_ADDRESS | SET_BAR_ENABLE;
+	pci_write_config32(LPC_BDF, PBASE, reg);
+	reg = IO_BASE_ADDRESS | SET_BAR_ENABLE;
+	pci_write_config32(LPC_BDF, IOBASE, reg);
+	reg = ILB_BASE_ADDRESS | SET_BAR_ENABLE;
+	pci_write_config32(LPC_BDF, IBASE, reg);
+	reg = SPI_BASE_ADDRESS | SET_BAR_ENABLE;
+	pci_write_config32(LPC_BDF, SBASE, reg);
+	reg = MPHY_BASE_ADDRESS | SET_BAR_ENABLE;
+	pci_write_config32(LPC_BDF, MPBASE, reg);
+	reg = PUNIT_BASE_ADDRESS | SET_BAR_ENABLE;
+	pci_write_config32(LPC_BDF, PUBASE, reg);
+	reg = RCBA_BASE_ADDRESS | RCBA_ENABLE;
+	pci_write_config32(LPC_BDF, RCBA, reg);
+
+	/* IO Port Registers. */
+	reg = ACPI_BASE_ADDRESS | SET_BAR_ENABLE;
+	pci_write_config32(LPC_BDF, ABASE, reg);
+	reg = GPIO_BASE_ADDRESS | SET_BAR_ENABLE;
+	pci_write_config32(LPC_BDF, GBASE, reg);
+}
+
+static void spi_init(void)
+{
+	const uint32_t scs = SPI_BASE_ADDRESS + SCS;
+	const uint32_t bcr = SPI_BASE_ADDRESS + BCR;
+	uint32_t reg;
+
+	/* Disable generating SMI when setting WPD bit. */
+	write32(scs, read32(scs) & ~SMIWPEN);
+	/*
+	 * Enable caching and prefetching in the SPI controller. Disable
+	 * the SMM-only BIOS write and set WPD bit.
+	 */
+	reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD;
+	reg &= ~EISS;
+	write32(bcr, reg);
+}
+
+static void baytrail_rtc_init(void)
+{
+	uint32_t pbase = pci_read_config32(LPC_BDF, PBASE) & 0xfffffff0;
+	uint32_t gen_pmcon1 = read32(pbase + GEN_PMCON1);
+	int rtc_failed = !!(gen_pmcon1 & RPS);
+
+	if (rtc_failed) {
+		printk(BIOS_DEBUG,
+			"RTC Failure detected.  Resetting Date to %x/%x/%x%x\n",
+			COREBOOT_BUILD_MONTH_BCD,
+			COREBOOT_BUILD_DAY_BCD,
+			0x20,
+			COREBOOT_BUILD_YEAR_BCD);
+
+		write32(DEFAULT_PBASE + GEN_PMCON1, gen_pmcon1 & ~RPS);
+	}
+
+	rtc_init(rtc_failed);
+}
+
+/* Entry from cache-as-ram.inc. */
+void * asmlinkage main(FSP_INFO_HEADER *fsp_info_header)
+{
+	const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS;
+	const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2;
+	uint32_t fd_mask = 0;
+	uint32_t fd2_mask = 0;
+
+	post_code(0x40);
+
+	program_base_addresses();
+
+	post_code(0x41);
+	tco_disable();
+
+	post_code(0x42);
+	byt_config_com1_and_enable();
+
+	post_code(0x43);
+	console_init();
+
+	spi_init();
+	baytrail_rtc_init();
+
+	/* Call into mainboard. */
+	early_mainboard_romstage_entry();
+
+	set_max_freq();
+
+	post_code(0x44);
+
+	/* Program any required function disables */
+	get_func_disables(&fd_mask, &fd2_mask);
+
+	if (fd_mask != 0) {
+		write32(func_dis, read32(func_dis) | fd_mask);
+		/* Ensure posted write hits. */
+		read32(func_dis);
+	}
+
+	if (fd2_mask != 0) {
+		write32(func_dis2, read32(func_dis2) | fd2_mask);
+		/* Ensure posted write hits. */
+		read32(func_dis2);
+	}
+
+	post_code(0x47);
+
+  /*
+   * Call early init to initialize memory and chipset. This function returns
+   * to the romstage_main_continue function with a pointer to the HOB
+   * structure.
+   */
+	post_code(0x48);
+	printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n");
+	fsp_early_init(fsp_info_header);
+	die("Uh Oh! fsp_early_init should not return here.\n");
+}
+
+/*******************************************************************************
+ * The FSP early_init function returns to this function.
+ * Memory is setup and the stack is set by the FSP.
+ */
+void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
+	int cbmem_was_initted;
+	void *cbmem_hob_ptr;
+
+#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)
+	tsc_t after_initram_time = rdtsc();
+	tsc_t base_time;
+	base_time.hi = 0;
+	base_time.lo = 0;
+#endif
+
+	post_code(0x4a);
+	printk(BIOS_DEBUG, "%s status: %x  hob_list_ptr: %x\n",
+		__func__, (u32) status, (u32) hob_list_ptr);
+
+#if IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE)
+	/* FSP reconfigures USB, so reinit it to have debug */
+	usbdebug_init();
+#endif	/* IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) */
+
+	printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status);
+
+	report_platform_info();
+
+#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)
+	after_initram_time = rdtsc();
+#endif
+	post_code(0x4b);
+
+	late_mainboard_romstage_entry();
+	post_code(0x4c);
+
+	quick_ram_check();
+	post_code(0x4d);
+
+	cbmem_was_initted = !cbmem_recovery(0);
+
+	/* Save the HOB pointer in CBMEM to be used in ramstage*/
+	cbmem_hob_ptr = cbmem_add (CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr));
+	*(u32*)cbmem_hob_ptr = (u32)hob_list_ptr;
+	post_code(0x4e);
+
+#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)
+	timestamp_init(base_time);
+	timestamp_reinit();
+	timestamp_add(TS_AFTER_INITRAM, after_initram_time);
+	timestamp_add_now(TS_END_ROMSTAGE);
+#endif
+
+#if IS_ENABLED(CONFIG_CONSOLE_CBMEM)
+	printk(BIOS_DEBUG, "cbmemc_reinit\n");
+	cbmemc_reinit();
+#endif
+	post_code(0x4f);
+
+	/* Load the ramstage. */
+	copy_and_run();
+	while (1);
+}
diff --git a/src/soc/intel/fsp_baytrail/romstage/uart.c b/src/soc/intel/fsp_baytrail/romstage/uart.c
new file mode 100644
index 0000000000..971067f143
--- /dev/null
+++ b/src/soc/intel/fsp_baytrail/romstage/uart.c
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <baytrail/gpio.h>
+#include <baytrail/iomap.h>
+#include <baytrail/lpc.h>
+#include <baytrail/pci_devs.h>
+#include <baytrail/romstage.h>
+
+void byt_config_com1_and_enable(void)
+{
+	uint32_t reg;
+
+	/* Enable the legacy UART hardware. */
+	reg = 1;
+	pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg);
+
+	/* Set up the pads to select the UART function */
+	score_select_func(UART_RXD_PAD, 1);
+	score_select_func(UART_TXD_PAD, 1);
+}