diff options
| author | Kevin Paul Herbert <kph@meraki.net> | 2014-12-24 18:43:20 -0800 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-02-15 08:50:22 +0100 |
| commit | bde6d309dfafe58732ec46314a2d4c08974b62d4 (patch) | |
| tree | 17ba00565487ddfbb5759c96adfbb3fffe2a4550 /src/soc/intel/fsp_baytrail/romstage/romstage.c | |
| parent | 4b10dec1a66122b515b2191f823d7fd379ec655f (diff) | |
x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.
Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/fsp_baytrail/romstage/romstage.c')
| -rw-r--r-- | src/soc/intel/fsp_baytrail/romstage/romstage.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index e487a25e86..81a02795ab 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -56,7 +56,7 @@ uint32_t chipset_prev_sleep_state(uint32_t clear) /* Read Power State */ pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); - gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1); + gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); printk(BIOS_DEBUG, "PM1_STS = 0x%x PM1_CNT = 0x%x GEN_PMCON1 = 0x%x\n", pm1_sts, pm1_cnt, gen_pmcon1); @@ -118,8 +118,8 @@ static void program_base_addresses(void) static void spi_init(void) { - const uint32_t scs = SPI_BASE_ADDRESS + SCS; - const uint32_t bcr = SPI_BASE_ADDRESS + BCR; + uint32_t *scs = (uint32_t *)(SPI_BASE_ADDRESS + SCS); + uint32_t *bcr = (uint32_t *)(SPI_BASE_ADDRESS + BCR); uint32_t reg; /* Disable generating SMI when setting WPD bit. */ @@ -135,8 +135,8 @@ static void spi_init(void) static void baytrail_rtc_init(void) { - uint32_t pbase = pci_read_config32(LPC_BDF, PBASE) & 0xfffffff0; - uint32_t gen_pmcon1 = read32(pbase + GEN_PMCON1); + uint32_t *pbase = (uint32_t *)(pci_read_config32(LPC_BDF, PBASE) & 0xfffffff0); + uint32_t gen_pmcon1 = read32(pbase + (GEN_PMCON1/sizeof(u32))); int rtc_failed = !!(gen_pmcon1 & RPS); if (rtc_failed) { @@ -144,7 +144,7 @@ static void baytrail_rtc_init(void) "RTC Failure detected. Resetting Date to %s\n", coreboot_dmi_date); - write32(DEFAULT_PBASE + GEN_PMCON1, gen_pmcon1 & ~RPS); + write32((uint32_t *)(DEFAULT_PBASE + GEN_PMCON1), gen_pmcon1 & ~RPS); } cmos_init(rtc_failed); @@ -153,8 +153,8 @@ static void baytrail_rtc_init(void) /* Entry from cache-as-ram.inc. */ void main(FSP_INFO_HEADER *fsp_info_header) { - const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS; - const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2; + uint32_t *func_dis = (uint32_t *)(PMC_BASE_ADDRESS + FUNC_DIS); + uint32_t *func_dis2 = (uint32_t *)(PMC_BASE_ADDRESS + FUNC_DIS2); uint32_t fd_mask = 0; uint32_t fd2_mask = 0; |