diff options
author | Martin Roth <gaumless@gmail.com> | 2014-05-12 21:55:00 -0600 |
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committer | Martin Roth <gaumless@gmail.com> | 2014-05-29 23:10:36 +0200 |
commit | 433659ad1e864808ec30e90a62ecfd711559c5a9 (patch) | |
tree | 9e9cd5ddffd7c75a7a3fc66c1fa9422a40625989 /src/soc/intel/fsp_baytrail/raminit.c | |
parent | 2a9b2ed3ff5411d0efdbde3b9ba1d1de06ab09aa (diff) |
fsp_baytrail: Add the FSP version of Intel's Bay Trail-I chip
While similar to the Bay Trail-M/D code based on the MRC, there are
many differences as well:
- Obviously, uses the FSP instead of the MRC binaries.
- FSP does additional hardware setup, so coreboot doesn't need to.
- Different microcode & microcode loading method
- Uses the cache_as_ram.inc from the FSP Driver
- Various other changes in support of the FSP
Additional changes that don't have to to with the FSP vs MRC:
- Updated IRQ Routing
- Different FADT implementation.
This was validated with FSP:
BAYTRAIL_FSP_GOLD_002_10-JANUARY-2014.fd
SHA256: d29eefbb33454bd5314bfaa38fb055d592a757de7b348ed7096cd8c2d65908a5
MD5: 9360cd915f0d3e4116bbc782233d7b91
Change-Id: Iadadf8cd6cf444ba840e0f76d3aed7825cd7aee4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5791
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/fsp_baytrail/raminit.c')
-rw-r--r-- | src/soc/intel/fsp_baytrail/raminit.c | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/src/soc/intel/fsp_baytrail/raminit.c b/src/soc/intel/fsp_baytrail/raminit.c new file mode 100644 index 0000000000..9170f483ca --- /dev/null +++ b/src/soc/intel/fsp_baytrail/raminit.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/io.h> +#include <cbmem.h> +#include <device/device.h> +#include <baytrail/baytrail.h> +#include <baytrail/iosf.h> +#include <cpu/x86/msr.h> +#include <drivers/intel/fsp/fsp_util.h> + +unsigned long get_top_of_ram(void) +{ + /* + * Calculate the top of usable (low) DRAM. + * The FSP's reserved memory sits just below the SMM region, + * allowing calculation of the top of usable memory. + * + * The entire memory map is shown in northcluster.c + */ + u32 tom = iosf_bunit_read(BUNIT_BMBOUND); + u32 bsmmrrl = iosf_bunit_read(BUNIT_SMRRL) << 20; + if (bsmmrrl) { + tom = bsmmrrl; + } + tom -= FSP_RESERVE_MEMORY_SIZE; + + return (unsigned long) tom; +} + |