diff options
| author | Joel Kitching <kitching@google.com> | 2018-08-17 15:38:59 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-08-22 15:33:50 +0000 |
| commit | 44cff7a8975b2adbf2866718ec8c61ab0d9bd505 (patch) | |
| tree | 92d4975db05b7dde5b861f03e5ee3c65bbb6b661 /src/soc/intel/fsp_baytrail/include | |
| parent | 5846d5727a05e395d13317daba049e0e56e15d33 (diff) | |
cbtable: remove chromeos_acpi from cbtable
Since we can derive chromeos_acpi's location from that of
ACPI GNVS, remove chromeos_acpi entry from cbtable and
instead use acpi_gnvs + GVNS_CHROMEOS_ACPI_OFFSET.
BUG=b:112288216
TEST=None
CQ-DEPEND=CL:1179725
Change-Id: I74d8a9965a0ed7874ff03884e7a921fd725eace9
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/28190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/fsp_baytrail/include')
| -rw-r--r-- | src/soc/intel/fsp_baytrail/include/soc/device_nvs.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h b/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h index 5bafea6fd0..8eff8cdb6f 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h +++ b/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h @@ -19,9 +19,6 @@ #include <stdint.h> #include <compiler.h> -/* Offset in Global NVS where this structure lives */ -#define DEVICE_NVS_OFFSET 0x1000 - #define LPSS_NVS_SIO_DMA1 0 #define LPSS_NVS_I2C1 1 #define LPSS_NVS_I2C2 2 |