diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2016-07-13 23:22:01 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-15 08:33:03 +0200 |
| commit | 15e439a72e26b72394b14e3777541819468bc10c (patch) | |
| tree | 0b70bf36407656572248332e647b33636d0ca66f /src/soc/intel/fsp_baytrail/include | |
| parent | 9e6d143a82a852ddfa64f20ceb8695939c1dace1 (diff) | |
soc/intel/fsp_baytrail: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.
BUG=chrome-os-partner:54977
Change-Id: I1ff1517ded2d43e3790d980599e756d0d064f75c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15674
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/fsp_baytrail/include')
| -rw-r--r-- | src/soc/intel/fsp_baytrail/include/soc/pmc.h | 9 |
1 files changed, 1 insertions, 8 deletions
diff --git a/src/soc/intel/fsp_baytrail/include/soc/pmc.h b/src/soc/intel/fsp_baytrail/include/soc/pmc.h index 1652e86c16..d5b1c44cc5 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/pmc.h +++ b/src/soc/intel/fsp_baytrail/include/soc/pmc.h @@ -17,6 +17,7 @@ #ifndef _BAYTRAIL_PMC_H_ #define _BAYTRAIL_PMC_H_ +#include <arch/acpi.h> #define IOCOM1 0x3f8 @@ -148,14 +149,6 @@ #define GBL_EN (1 << 5) #define TMROF_EN (1 << 0) #define PM1_CNT 0x04 -#define SLP_EN (1 << 13) -#define SLP_TYP_SHIFT 10 -#define SLP_TYP (7 << SLP_TYP_SHIFT) -#define SLP_TYP_S0 0 -#define SLP_TYP_S1 1 -#define SLP_TYP_S3 5 -#define SLP_TYP_S4 6 -#define SLP_TYP_S5 7 #define GBL_RLS (1 << 2) #define BM_RLD (1 << 1) #define SCI_EN (1 << 0) |