soc/intel/fsp_baytrail: Drop support

Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.

Change-Id: I0b0344f1ebed12207a77c985f27893a1353c0925
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>

1 files changed, 0 insertions, 78 deletions

diff --git a/src/soc/intel/fsp_baytrail/chip.c b/src/soc/intel/fsp_baytrail/chip.c
deleted file mode 100644
index 3ca26add30..0000000000
--- a/src/soc/intel/fsp_baytrail/chip.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <soc/pci_devs.h>
-#include <soc/ramstage.h>
-#include <drivers/intel/fsp1_0/fsp_util.h>
-#include "chip.h"
-
-static void pci_domain_set_resources(struct device *dev)
-{
-	assign_resources(dev->link_list);
-}
-
-static struct device_operations pci_domain_ops = {
-	.read_resources   = pci_domain_read_resources,
-	.set_resources    = pci_domain_set_resources,
-	.enable_resources = NULL,
-	.init             = NULL,
-	.scan_bus         = pci_domain_scan_bus,
-};
-
-static struct device_operations cpu_bus_ops = {
-	.read_resources   = DEVICE_NOOP,
-	.set_resources    = DEVICE_NOOP,
-	.enable_resources = DEVICE_NOOP,
-	.init             = baytrail_init_cpus,
-	.scan_bus         = NULL,
-};
-
-static void enable_dev(struct device *dev)
-{
-	printk(BIOS_DEBUG, "enable_dev(%s, %d)\n",
-	       dev_name(dev), dev->path.type);
-
-	/* Set the operations if it is a special bus type */
-	if (dev->path.type == DEVICE_PATH_DOMAIN) {
-		dev->ops = &pci_domain_ops;
-	} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
-		dev->ops = &cpu_bus_ops;
-	} else if (dev->path.type == DEVICE_PATH_PCI) {
-		/* Handle south cluster enablement. */
-		if (PCI_SLOT(dev->path.pci.devfn) > GFX_DEV &&
-		    (dev->ops == NULL || dev->ops->enable == NULL)) {
-			southcluster_enable_dev(dev);
-		}
-	}
-}
-
-/* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */
-static void soc_init(void *chip_info)
-{
-	baytrail_init_pre_device();
-}
-
-struct chip_operations soc_intel_fsp_baytrail_ops = {
-	CHIP_NAME("Intel BayTrail SoC")
-	.enable_dev = enable_dev,
-	.init = soc_init,
-};
-
-struct pci_operations soc_pci_ops = {
-	.set_subsystem = &pci_dev_set_subsystem,
-};