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| author | Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com> | 2019-10-25 18:13:44 +0800 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-10-26 15:16:59 +0000 |
| commit | a9e07f94448650b3a9a27062775c642f8939464b (patch) | |
| tree | cdf1b5b3a3912ce40354f3ee13b4fa29cb2088a2 /src/soc/intel/fsp_baytrail/chip.c | |
| parent | 5e779f9a6c56dd9135fc2662c7a81cb1906b0f81 (diff) | |
mb/intel/saddlebrook: Enable serial port on SIO
Enable saddlebrook board Serial port on SuperIO by
selecting DRIVERS_UART_8250IO.
TEST=Build, Boot saddlebrook board and verified serial logs.
Change-Id: Ic7b3416f281bfd91416c987c5a720ffac0c89d45
Signed-off-by: Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner
Diffstat (limited to 'src/soc/intel/fsp_baytrail/chip.c')
0 files changed, 0 insertions, 0 deletions