fsp_baytrail: Initialize LPC pads in bootblock for port 80

Port 80h codes were coming out of bootblock and romstage scrambled, or
were not coming out at all.  Initializing the LPC signal pads as LPC
fixes that issue.

Change-Id: I16943513f2eb6fe8fa58766aaa82dac182440c34
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7802
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@gmx.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 15 insertions, 0 deletions

diff --git a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c
index 1623f04da1..e8f5572ef7 100644
--- a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c
+++ b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c
@@ -27,6 +27,7 @@
 #include <baytrail/spi.h>
 #include <baytrail/iomap.h>
 #include <baytrail/lpc.h>
+#include <baytrail/gpio.h>
 #include <reset.h>
 
 /*
@@ -100,6 +101,19 @@ static void setup_mmconfig(void)
 	pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg);
 }
 
+static const uint8_t lpc_pads[12] = {
+	70, 68, 67, 66, 69, 71, 65, 72, 86, 90, 88, 92,
+};
+
+static void set_up_lpc_pads(void)
+{
+	uint32_t reg = IO_BASE_ADDRESS | SET_BAR_ENABLE;
+	pci_write_config32(LPC_BDF, IOBASE, reg);
+
+	for (reg = 0; reg < 12; reg++)
+		score_select_func(lpc_pads[reg], 1);
+}
+
 static void bootblock_cpu_init(void)
 {
 
@@ -109,4 +123,5 @@ static void bootblock_cpu_init(void)
 	setup_mmconfig();
 	enable_rom_caching();
 	enable_spi_prefetch();
+	set_up_lpc_pads();
 }