diff options
| author | Werner Zeh <werner.zeh@siemens.com> | 2022-10-20 15:57:42 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-10-25 15:06:18 +0000 |
| commit | cd906960df03aeed28134e58bbbefdd981eb8bd2 (patch) | |
| tree | 1e521babda4c7f330f55f93b6312f8f19ab9a08f /src/soc/intel/elkhartlake | |
| parent | f61070e87c80e75793f755a544f6f2f5465a9cc8 (diff) | |
soc/intel/elkhartlake: Fix incorrect divider for MDIO clock
After some measurements it turned out that Elkhart Lake uses a higher
CSR clock internally from which the MDIO clock is derived. In order to
stay compliant with the specification, the MDIO clock needs to be lower
than 2.5 MHz. Therefore, the divider needs to be 102 and not 62.
This patch changes the define to match the new divider value and uses
this new define at the appropriate place.
Test=Measure the MDIO clock rate on mc_ehl2 which results in 2 MHz.
Change-Id: Idf498c3547530dfa395f54488ef244e787062e34
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Diffstat (limited to 'src/soc/intel/elkhartlake')
| -rw-r--r-- | src/soc/intel/elkhartlake/include/soc/tsn_gbe.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/elkhartlake/tsn_gbe.c | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/elkhartlake/include/soc/tsn_gbe.h b/src/soc/intel/elkhartlake/include/soc/tsn_gbe.h index b1d04cccd2..cd9f12ee11 100644 --- a/src/soc/intel/elkhartlake/include/soc/tsn_gbe.h +++ b/src/soc/intel/elkhartlake/include/soc/tsn_gbe.h @@ -15,7 +15,7 @@ #define TSN_MAC_PHYAD(pa) (pa << 21) /* Physical Layer Address */ #define TSN_MAC_REGAD(rda) (rda << 16) /* Register/Device Address */ #define TSN_MAC_CLK_TRAIL_4 (4 << 12) /* 4 Trailing Clocks */ -#define TSN_MAC_CSR_CLK_DIV_62 (1 << 8) /* 0001: CSR=100-150 MHz; CSR/62 */ +#define TSN_MAC_CSR_CLK_DIV_102 (1 << 10) /* 0100: CSR=150-250 MHz; CSR/102 */ #define TSN_MAC_OP_CMD_WRITE (1 << 2) /* GMII Operation Command Write */ #define TSN_MAC_OP_CMD_READ (3 << 2) /* GMII Operation Command Read */ #define TSN_MAC_GMII_BUSY (1 << 0) /* GMII Busy bit */ diff --git a/src/soc/intel/elkhartlake/tsn_gbe.c b/src/soc/intel/elkhartlake/tsn_gbe.c index 3e08897c5c..2a1468c4f2 100644 --- a/src/soc/intel/elkhartlake/tsn_gbe.c +++ b/src/soc/intel/elkhartlake/tsn_gbe.c @@ -52,7 +52,7 @@ uint16_t tsn_mdio_read(void *base, uint8_t phy_adr, uint8_t reg_adr) clrsetbits32(base + TSN_MAC_MDIO_ADR, TSN_MAC_MDIO_ADR_MASK, TSN_MAC_PHYAD(phy_adr) | TSN_MAC_REGAD(reg_adr) - | TSN_MAC_CLK_TRAIL_4 | TSN_MAC_CSR_CLK_DIV_62 + | TSN_MAC_CLK_TRAIL_4 | TSN_MAC_CSR_CLK_DIV_102 | TSN_MAC_OP_CMD_READ | TSN_MAC_GMII_BUSY); /* Wait for MDIO frame transfer to complete before reading MDIO DATA register */ @@ -75,7 +75,7 @@ void tsn_mdio_write(void *base, uint8_t phy_adr, uint8_t reg_adr, uint16_t data) write16(base + TSN_MAC_MDIO_DATA, data); clrsetbits32(base + TSN_MAC_MDIO_ADR, TSN_MAC_MDIO_ADR_MASK, TSN_MAC_PHYAD(phy_adr) | TSN_MAC_REGAD(reg_adr) - | TSN_MAC_CLK_TRAIL_4 | TSN_MAC_CSR_CLK_DIV_62 + | TSN_MAC_CLK_TRAIL_4 | TSN_MAC_CSR_CLK_DIV_102 | TSN_MAC_OP_CMD_WRITE | TSN_MAC_GMII_BUSY); /* Wait for MDIO frame transfer to complete before do next */ |