diff options
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2022-04-27 11:24:05 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-05-21 17:40:52 +0000 |
| commit | dccdaceb494fdb0466a1c46b68df3642280f587f (patch) | |
| tree | f9fde441a368a3a17c40720865bcc5ba9f3c9e7d /src/soc/intel/elkhartlake/include | |
| parent | 8698a6f5a9d656c165f594cb9cd532a80d8e5e99 (diff) | |
soc/intel/ehl: Provide function to change PHY-to-MAC IRQ polarity
EHL MAC side expects a rising edge signal for an IRQ. Based on the
mainboard wiring it could be necessary to change the interrupt polarity.
This patch provides the functionality to invert a falling edge signal
that comes from an external PHY. The inverting can be activated via
devicetree parameter.
Change-Id: Ia314014c7cacbeb72629c773c8c0bb5f002a3f54
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc/intel/elkhartlake/include')
| -rw-r--r-- | src/soc/intel/elkhartlake/include/soc/tsn_gbe.h | 31 |
1 files changed, 28 insertions, 3 deletions
diff --git a/src/soc/intel/elkhartlake/include/soc/tsn_gbe.h b/src/soc/intel/elkhartlake/include/soc/tsn_gbe.h index e9f6c8d1fe..b1d04cccd2 100644 --- a/src/soc/intel/elkhartlake/include/soc/tsn_gbe.h +++ b/src/soc/intel/elkhartlake/include/soc/tsn_gbe.h @@ -3,13 +3,38 @@ #ifndef _SOC_ELKHARTLAKE_TSN_GBE_H_ #define _SOC_ELKHARTLAKE_TSN_GBE_H_ -#define MAC_ADDR_LEN 6 +#define MAC_ADDR_LEN 6 -#define TSN_MAC_ADD0_HIGH 0x300 /* MAC Address0 High register */ -#define TSN_MAC_ADD0_LOW 0x304 /* MAC Address0 Low register */ +#define TSN_MAC_ADD0_HIGH 0x300 /* MAC Address0 High register */ +#define TSN_MAC_ADD0_LOW 0x304 /* MAC Address0 Low register */ + +#define TSN_GMII_TIMEOUT_MS 20 + +#define TSN_MAC_MDIO_ADR 0x200 /* MAC MDIO Address register */ +#define TSN_MAC_MDIO_ADR_MASK 0x03FF7F0E +#define TSN_MAC_PHYAD(pa) (pa << 21) /* Physical Layer Address */ +#define TSN_MAC_REGAD(rda) (rda << 16) /* Register/Device Address */ +#define TSN_MAC_CLK_TRAIL_4 (4 << 12) /* 4 Trailing Clocks */ +#define TSN_MAC_CSR_CLK_DIV_62 (1 << 8) /* 0001: CSR=100-150 MHz; CSR/62 */ +#define TSN_MAC_OP_CMD_WRITE (1 << 2) /* GMII Operation Command Write */ +#define TSN_MAC_OP_CMD_READ (3 << 2) /* GMII Operation Command Read */ +#define TSN_MAC_GMII_BUSY (1 << 0) /* GMII Busy bit */ + +/* MDIO - Adhoc PHY Sublayer Register */ +#define TSN_MAC_MDIO_ADHOC_ADR 0x15 +/* Global Configuration Register */ +#define TSN_MAC_MDIO_GCR 0x0 +/* PHY to MAC Interrupt Polarity bit */ +#define TSN_MAC_PHY2MAC_INTR_POL (1 << 6) + +#define TSN_MAC_MDIO_DATA 0x204 /* MAC MDIO Data register */ /* We need one function we can call to get a MAC address to use. */ /* This function can be coded somewhere else but must exist. */ enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[MAC_ADDR_LEN]); +enum cb_err phy_gmii_ready(void *base); +uint16_t tsn_mdio_read(void *base, uint8_t phy_adr, uint8_t reg_adr); +void tsn_mdio_write(void *base, uint8_t phy_adr, uint8_t reg_adr, uint16_t data); + #endif /* _SOC_ELKHARTLAKE_TSN_GBE_H_ */ |