diff options
| author | Lean Sheng Tan <lean.sheng.tan@intel.com> | 2021-06-15 22:05:42 -0700 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-06-18 06:03:25 +0000 |
| commit | 8bbff1f55494db50b92306a5f65c634c87e9c9d7 (patch) | |
| tree | 514400fc04336a74377061f8ada672ac645ea35f /src/soc/intel/elkhartlake/fsp_params.c | |
| parent | fefc2ea4c41a1a786fb0b0dc890da1d1370f0731 (diff) | |
soc/intel/elkhartlake: Make use of FSP_ARRAY_LOAD macro
Use FSP_ARRAY_LOAD macro for checking and loading array type
configs into array type UPDs to increase readability.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I2562977e55f8909038697f7e19b82ec6b5e47fae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc/intel/elkhartlake/fsp_params.c')
| -rw-r--r-- | src/soc/intel/elkhartlake/fsp_params.c | 48 |
1 files changed, 9 insertions, 39 deletions
diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index f61bfa7618..9797728bf4 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -66,53 +66,23 @@ static void parse_devicetree(FSP_S_CONFIG *params) /* LPSS controllers configuration */ /* I2C */ - _Static_assert(ARRAY_SIZE(params->SerialIoI2cMode) >= - ARRAY_SIZE(config->SerialIoI2cMode), "copy buffer overflow!"); - memcpy(params->SerialIoI2cMode, config->SerialIoI2cMode, - sizeof(config->SerialIoI2cMode)); - - _Static_assert(ARRAY_SIZE(params->PchSerialIoI2cPadsTermination) >= - ARRAY_SIZE(config->SerialIoI2cPadsTermination), - "copy buffer overflow!"); - memcpy(params->PchSerialIoI2cPadsTermination, config->SerialIoI2cPadsTermination, - sizeof(config->SerialIoI2cPadsTermination)); + FSP_ARRAY_LOAD(params->SerialIoI2cMode, config->SerialIoI2cMode); + FSP_ARRAY_LOAD(params->PchSerialIoI2cPadsTermination, + config->SerialIoI2cPadsTermination); params->PchSerialIoI2cSclPinMux[4] = 0x1B44AC09; //GPIO native mode for GPP_H9 params->PchSerialIoI2cSdaPinMux[4] = 0x1B44CC08; //GPIO native mode for GPP_H8 /* GSPI */ - _Static_assert(ARRAY_SIZE(params->SerialIoSpiMode) >= - ARRAY_SIZE(config->SerialIoGSpiMode), "copy buffer overflow!"); - memcpy(params->SerialIoSpiMode, config->SerialIoGSpiMode, - sizeof(config->SerialIoGSpiMode)); - - _Static_assert(ARRAY_SIZE(params->SerialIoSpiCsEnable) >= - ARRAY_SIZE(config->SerialIoGSpiCsEnable), "copy buffer overflow!"); - memcpy(params->SerialIoSpiCsEnable, config->SerialIoGSpiCsEnable, - sizeof(config->SerialIoGSpiCsEnable)); - - _Static_assert(ARRAY_SIZE(params->SerialIoSpiCsMode) >= - ARRAY_SIZE(config->SerialIoGSpiCsMode), "copy buffer overflow!"); - memcpy(params->SerialIoSpiCsMode, config->SerialIoGSpiCsMode, - sizeof(config->SerialIoGSpiCsMode)); - - _Static_assert(ARRAY_SIZE(params->SerialIoSpiCsState) >= - ARRAY_SIZE(config->SerialIoGSpiCsState), "copy buffer overflow!"); - memcpy(params->SerialIoSpiCsState, config->SerialIoGSpiCsState, - sizeof(config->SerialIoGSpiCsState)); - + FSP_ARRAY_LOAD(params->SerialIoSpiMode, config->SerialIoGSpiMode); + FSP_ARRAY_LOAD(params->SerialIoSpiCsEnable, config->SerialIoGSpiCsEnable); + FSP_ARRAY_LOAD(params->SerialIoSpiCsMode, config->SerialIoGSpiCsMode); + FSP_ARRAY_LOAD(params->SerialIoSpiCsState, config->SerialIoGSpiCsState); params->SerialIoSpiCsPolarity[2] = 0; /* UART */ - _Static_assert(ARRAY_SIZE(params->SerialIoUartMode) >= - ARRAY_SIZE(config->SerialIoUartMode), "copy buffer overflow!"); - memcpy(params->SerialIoUartMode, config->SerialIoUartMode, - sizeof(config->SerialIoUartMode)); - - _Static_assert(ARRAY_SIZE(params->SerialIoUartDmaEnable) >= - ARRAY_SIZE(config->SerialIoUartDmaEnable), "copy buffer overflow!"); - memcpy(params->SerialIoUartDmaEnable, config->SerialIoUartDmaEnable, - sizeof(config->SerialIoUartDmaEnable)); + FSP_ARRAY_LOAD(params->SerialIoUartMode, config->SerialIoUartMode); + FSP_ARRAY_LOAD(params->SerialIoUartDmaEnable, config->SerialIoUartDmaEnable); params->SerialIoUartCtsPinMuxPolicy[0] = 0x2B01320F; //GPIO native mode for GPP_T15 params->SerialIoUartRtsPinMuxPolicy[0] = 0x2B01220E; //GPIO native mode for GPP_T14 |