diff options
| author | Lean Sheng Tan <lean.sheng.tan@intel.com> | 2021-06-08 23:41:15 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-06-11 07:32:17 +0000 |
| commit | 0cdcdc736ea28be7bfc6eabdac2430ecf6ee409c (patch) | |
| tree | 5664b5a7f0b3712ba843892cd4f05e58f1ab48f8 /src/soc/intel/elkhartlake/fsp_params.c | |
| parent | dea42e011a126c4fdc9ab62f6d6c449df4740f82 (diff) | |
soc/intel/elkhartlake: Update FSP-S FuSa related settings
Further add initial Silicon UPD settings for FuSa
(Functional Safety). Disable all by default, due to FSP binary
enable all by default.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I88264ba3e3f9f54ad949c55b230082d1fa289fa4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55342
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/elkhartlake/fsp_params.c')
| -rw-r--r-- | src/soc/intel/elkhartlake/fsp_params.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 213fc8c7f1..2a8b07e45f 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -344,6 +344,14 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchFivrVccinAuxOffToHighCurModeVolTranTime = 0x0096; params->FivrSpreadSpectrum = 0xF; + /* FuSa (Functional Safety) config */ + if (!config->FuSaEnable) { + params->DisplayFusaConfigEnable = 0; + params->GraphicFusaConfigEnable = 0; + params->OpioFusaConfigEnable = 0; + params->PsfFusaConfigEnable = 0; + } + /* Override/Fill FSP Silicon Param for mainboard */ mainboard_silicon_init_params(params); } |