soc/intel/elkhartlake: Do initial SoC commit till ramstage

Clone entirely from Jasperlake

List of changes on top off initial jasperlake clone
1. Replace "Jasperlake" with "Elkhartlake"
2. Replace "jsl" with "ehl"
3. Replace "jsp" with "mcc"
4. Rename structure based on Jasperlake with Elkhartlake
5. Clean up upd override in fsp_params.c will be added later
6. Sort #include files alphabetically as per comment
7. Remove doc details from espi.c until it is ready
8. Remove pch_isclk & camera clocks related codes
9. Add new #define NMI_STS_CNT & NMI_EN as per comment

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I372b0bb5912e013445ed8df7c58d0a9ee9a7cf35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

1 files changed, 79 insertions, 0 deletions

diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c
new file mode 100644
index 0000000000..3d740fb74c
--- /dev/null
+++ b/src/soc/intel/elkhartlake/fsp_params.c
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#include <assert.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <fsp/api.h>
+#include <fsp/ppi/mp_service_ppi.h>
+#include <fsp/util.h>
+#include <intelblocks/lpss.h>
+#include <intelblocks/mp_init.h>
+#include <intelblocks/xdci.h>
+#include <intelpch/lockdown.h>
+#include <soc/intel/common/vbt.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
+#include <soc/soc_chip.h>
+#include <string.h>
+
+/*
+ * ME End of Post configuration
+ * 0 - Disable EOP.
+ * 1 - Send in PEI (Applicable for FSP in API mode)
+ * 2 - Send in DXE (Not applicable for FSP in API mode)
+ */
+enum {
+	EOP_DISABLE,
+	EOP_PEI,
+	EOP_DXE,
+} EndOfPost;
+
+static const pci_devfn_t serial_io_dev[] = {
+	PCH_DEVFN_I2C0,
+	PCH_DEVFN_I2C1,
+	PCH_DEVFN_I2C2,
+	PCH_DEVFN_I2C3,
+	PCH_DEVFN_I2C4,
+	PCH_DEVFN_I2C5,
+	PCH_DEVFN_GSPI0,
+	PCH_DEVFN_GSPI1,
+	PCH_DEVFN_GSPI2,
+	PCH_DEVFN_UART0,
+	PCH_DEVFN_UART1,
+	PCH_DEVFN_UART2
+};
+
+static void parse_devicetree(FSP_S_CONFIG *params)
+{
+	const struct soc_intel_elkhartlake_config *config = config_of_soc();
+	/* TODO: Update with UPD override as FSP matures */
+}
+
+/* UPD parameters to be initialized before SiliconInit */
+void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
+{
+	unsigned int i;
+	struct device *dev;
+	FSP_S_CONFIG *params = &supd->FspsConfig;
+	struct soc_intel_elkhartlake_config *config = config_of_soc();
+
+	/* Parse device tree and fill in FSP UPDs */
+	parse_devicetree(params);
+
+	/* TODO: Update with UPD override as FSP matures */
+
+	/* Override/Fill FSP Silicon Param for mainboard */
+	mainboard_silicon_init_params(params);
+}
+
+/* Mainboard GPIO Configuration */
+__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
+
+/* Return list of SOC LPSS controllers */
+const pci_devfn_t *soc_lpss_controllers_list(size_t *size)
+{
+	*size = ARRAY_SIZE(serial_io_dev);
+	return serial_io_dev;
+}