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authorTan, Lean Sheng <lean.sheng.tan@intel.com>2021-05-26 06:40:56 -0700
committerPatrick Georgi <pgeorgi@google.com>2021-06-01 05:58:39 +0000
commit09133c78dd2c5753802bcf5b7e7eb9b5be9ecf6d (patch)
tree72bd269e79922481dc71c7c81606836609a8ffa0 /src/soc/intel/elkhartlake/chip.h
parentcdb81500f1fbfef2865e692e1193e39a56f9bca2 (diff)
soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs
Add Silicon upd settings for LPSS (GSPI/UART/I2C). Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Ib0c3cd1d37ff9892d09d6d86ac50e230549c7e53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc/intel/elkhartlake/chip.h')
-rw-r--r--src/soc/intel/elkhartlake/chip.h17
1 files changed, 17 insertions, 0 deletions
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h
index ce0984124d..6b36792bde 100644
--- a/src/soc/intel/elkhartlake/chip.h
+++ b/src/soc/intel/elkhartlake/chip.h
@@ -167,6 +167,14 @@ struct soc_intel_elkhartlake_config {
uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX];
/*
+ * UARTn Default DMA/PIO Mode Enable(1)/Disable(0):
+ */
+ uint8_t SerialIoUartDmaEnable[CONFIG_SOC_INTEL_UART_DEV_MAX];
+ /*
+ * GSPIn Default Chip Enable(1)/Disable(0):
+ */
+ uint8_t SerialIoGSpiCsEnable[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
+ /*
* GSPIn Default Chip Select Mode:
* 0:Hardware Mode,
* 1:Software Mode
@@ -178,6 +186,15 @@ struct soc_intel_elkhartlake_config {
* 1: High
*/
uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
+/*
+ * SerialIo I2C Pads Termination Config:
+ * 0x0:Hardware default,
+ * 0x1:None,
+ * 0x13:1kOhm weak pull-up,
+ * 0x15:5kOhm weak pull-up,
+ * 0x19:20kOhm weak pull-up
+ */
+ uint8_t SerialIoI2cPadsTermination[CONFIG_SOC_INTEL_I2C_DEV_MAX];
/*
* TraceHubMode config