diff options
| author | Lean Sheng Tan <lean.sheng.tan@intel.com> | 2021-06-09 13:58:12 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-25 16:09:18 +0000 |
| commit | 5cd7579ee54dbd9d424c6adc4b0228bcede95ffb (patch) | |
| tree | c23c481f7980325c6653db2f3b4aeff88e321cd4 /src/soc/intel/elkhartlake/Makefile.inc | |
| parent | 36425312ee8a04efa7582abfe143cb887e8ece30 (diff) | |
soc/intel/elkhartlake: Introduce Intel PSE
The Intel® Programmable Services Engine (Intel® PSE) is a
dedicated offload engine for IoT functions powered by an ARM
Cortex-M7 microcontroller. It provides independent, low-DMIPS
computing and low-speed I/Os for IoT applications, plus
dedicated services for real-time computing and time-sensitive
synchronization.
The PSE hosts new functions, including remote out-of-band
device management, network proxy, embedded controller lite
and sensor hub.
This CL enables the user to provide the base address of the
PSE FW blob which will then be loaded by the FSP-S onto the
ARM controller. PSE FW will do the initialization work of
PSE controller and its peripherals. The loading of PSE FW
should have negligible impact on boot time unless PSE
controller could not locate the PSE FW and FSP will attempt to
redo PSE FW loading and wait for PSE handshake until it times
out. Once PSE controller locate the PSE FW, it will do
initialization concurrently by itself with coreboot booting.
It also adds PSE related FSP-S UPD settings which enable the
setup of peripheral ownership (assigned to the PSE or x86
subsystem) and interrupts. These assignments need to take
place at a given point in the boot process and cannot be
changed later.
To verify if PSE FW is loaded properly, the user could enable
PchPseShellEnabled flag and the log will be printed at PSE UART
2.
For further info please refer to doc #611825 (for HW overview)
and #614110 (for PSE EDS).
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc/intel/elkhartlake/Makefile.inc')
| -rw-r--r-- | src/soc/intel/elkhartlake/Makefile.inc | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/soc/intel/elkhartlake/Makefile.inc b/src/soc/intel/elkhartlake/Makefile.inc index 6a5d5c7b0e..ce93e46e79 100644 --- a/src/soc/intel/elkhartlake/Makefile.inc +++ b/src/soc/intel/elkhartlake/Makefile.inc @@ -51,5 +51,18 @@ CPPFLAGS_common += -I$(src)/soc/intel/elkhartlake/include # B0 stepping cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-96-01 +cbfs-files-$(CONFIG_ADD_PSE_IMAGE_TO_CBFS) += pse.bin +pse.bin-file := $(CONFIG_PSE_IMAGE_FILE) +pse.bin-type := raw +pse.bin-compression := lzma + +# Add a build time check if the PSE file size fits +ifeq ($(CONFIG_ADD_PSE_IMAGE_TO_CBFS),y) +ifeq ($(call int-gt,\ + $(call file-size,$(CONFIG_PSE_IMAGE_FILE))\ + $(shell printf "%d" $(call int-shift-left, $(CONFIG_PSE_FW_FILE_SIZE_KIB) 10))), 1) +$(error PSE binary larger than CONFIG_PSE_FW_FILE_SIZE_KIB.) +endif +endif # CONFIG_ADD_PSE_IMAGE_TO_CBFS endif |