diff options
author | Nico Huber <nico.h@gmx.de> | 2018-10-04 23:42:42 +0200 |
---|---|---|
committer | Nico Huber <nico.h@gmx.de> | 2018-10-08 16:57:27 +0000 |
commit | d44221f9c8f3686e040ff9481829315068b321a3 (patch) | |
tree | 76337bf1cae88feda44e3c63dd7e32e964e8767d /src/soc/intel/denverton_ns | |
parent | 834543c0c71544b547194b093b8e1da990722762 (diff) |
Move compiler.h to commonlib
Its spreading copies got out of sync. And as it is not a standard header
but used in commonlib code, it belongs into commonlib. While we are at
it, always include it via GCC's `-include` switch.
Some Windows and BSD quirk handling went into the util copies. We always
guard from redefinitions now to prevent further issues.
Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/denverton_ns')
-rw-r--r-- | src/soc/intel/denverton_ns/acpi.c | 1 | ||||
-rw-r--r-- | src/soc/intel/denverton_ns/fiamux.c | 1 | ||||
-rw-r--r-- | src/soc/intel/denverton_ns/romstage.c | 1 |
3 files changed, 0 insertions, 3 deletions
diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 6a947ff83f..71e396004f 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -19,7 +19,6 @@ #include <arch/acpi.h> #include <arch/acpigen.h> #include <arch/smp/mpspec.h> -#include <compiler.h> #include <cpu/x86/smm.h> #include <string.h> #include <device/pci.h> diff --git a/src/soc/intel/denverton_ns/fiamux.c b/src/soc/intel/denverton_ns/fiamux.c index 418ccfa322..fc18a41312 100644 --- a/src/soc/intel/denverton_ns/fiamux.c +++ b/src/soc/intel/denverton_ns/fiamux.c @@ -15,7 +15,6 @@ * */ -#include <compiler.h> #include <console/console.h> #include <soc/fiamux.h> diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 3da349a63f..cf4ae7c1ed 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -15,7 +15,6 @@ */ #include <cbmem.h> -#include <compiler.h> #include <console/console.h> #include <cpu/x86/mtrr.h> #include <reset.h> |