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authorSubrata Banik <subratabanik@google.com>2022-02-15 20:49:01 +0530
committerFelix Held <felix-coreboot@felixheld.de>2022-02-18 20:23:33 +0000
commit7848aa9335e764952d50f05f9c66cfbf70291ec0 (patch)
tree6fadac698f452b428cb5222c23579f480e82d4c0 /src/soc/intel/denverton_ns/pmutil.c
parent95986169f93efe8b99c5b7d4a0fff3b5541d1377 (diff)
soc/intel/denverton_ns: Add function to clear PMCON status bits
This patch adds an SoC function to clear GEN_PMCON_A status bits to align with other IA coreboot implementations. Added `MS4V` macro for GEN_PMCON_A bit 18 as per EDS doc:558579. Additionally, removed `PMC_` prefix from PMC configuration register macros GEN_PMCON_A/B and ETR3. Moved PMC PCI device macro from pmc.h to pci_devs.h and name PCH_PMC_DEV to PCH_DEV_PMC. Also, adjust PCI macros under B0:D31:Fx based on function numbers. BUG=b:211954778 TEST=None. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I2690ccd387b40c0d89cf133117fd91914e1b71a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/soc/intel/denverton_ns/pmutil.c')
-rw-r--r--src/soc/intel/denverton_ns/pmutil.c23
1 files changed, 21 insertions, 2 deletions
diff --git a/src/soc/intel/denverton_ns/pmutil.c b/src/soc/intel/denverton_ns/pmutil.c
index 5a626449ac..822e50e397 100644
--- a/src/soc/intel/denverton_ns/pmutil.c
+++ b/src/soc/intel/denverton_ns/pmutil.c
@@ -1,12 +1,16 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#define __SIMPLE_DEVICE__
+
#include <stdint.h>
#include <arch/io.h>
#include <console/console.h>
-
+#include <device/pci.h>
+#include <intelblocks/pmclib.h>
#include <soc/iomap.h>
-#include <soc/soc_util.h>
+#include <soc/pci_devs.h>
#include <soc/pm.h>
+#include <soc/soc_util.h>
static void print_num_status_bits(int num_bits, uint32_t status,
const char *const bit_names[])
@@ -231,3 +235,18 @@ static uint32_t print_gpe_sts(uint32_t gpe_sts)
uint32_t clear_gpe_status(void) { return print_gpe_sts(reset_gpe_status()); }
void clear_pmc_status(void) { /* TODO */ }
+
+void pmc_clear_pmcon_sts(void)
+{
+ uint32_t reg_val;
+ const pci_devfn_t dev = PCH_DEV_PMC;
+
+ reg_val = pci_read_config32(dev, GEN_PMCON_A);
+ /*
+ * Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits
+ * while retaining MS4V write-1-to-clear bit
+ */
+ reg_val &= ~(MS4V);
+
+ pci_write_config32(dev, GEN_PMCON_A, reg_val);
+}