diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-02-15 20:49:01 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-18 20:23:33 +0000 |
| commit | 7848aa9335e764952d50f05f9c66cfbf70291ec0 (patch) | |
| tree | 6fadac698f452b428cb5222c23579f480e82d4c0 /src/soc/intel/denverton_ns/include | |
| parent | 95986169f93efe8b99c5b7d4a0fff3b5541d1377 (diff) | |
soc/intel/denverton_ns: Add function to clear PMCON status bits
This patch adds an SoC function to clear GEN_PMCON_A status bits to
align with other IA coreboot implementations.
Added `MS4V` macro for GEN_PMCON_A bit 18 as per EDS doc:558579.
Additionally, removed `PMC_` prefix from PMC configuration register
macros GEN_PMCON_A/B and ETR3.
Moved PMC PCI device macro from pmc.h to pci_devs.h and name PCH_PMC_DEV
to PCH_DEV_PMC. Also, adjust PCI macros under B0:D31:Fx based on
function numbers.
BUG=b:211954778
TEST=None.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I2690ccd387b40c0d89cf133117fd91914e1b71a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/soc/intel/denverton_ns/include')
| -rw-r--r-- | src/soc/intel/denverton_ns/include/soc/pci_devs.h | 6 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/include/soc/pm.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/include/soc/pmc.h | 20 |
3 files changed, 16 insertions, 13 deletions
diff --git a/src/soc/intel/denverton_ns/include/soc/pci_devs.h b/src/soc/intel/denverton_ns/include/soc/pci_devs.h index f1e120c339..a337b0d1e4 100644 --- a/src/soc/intel/denverton_ns/include/soc/pci_devs.h +++ b/src/soc/intel/denverton_ns/include/soc/pci_devs.h @@ -138,13 +138,15 @@ #define PCH_DEV_SLOT_LPC 0x1f #define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) +#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1) #define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2) #define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4) #define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5) #define PCH_DEV_LPC _PCH_DEV(LPC, 0) -#define PCH_DEV_SPI _PCH_DEV(LPC, 5) -#define PCH_DEV_P2SB _PCH_DEV(LPC, 1) +#define PCH_DEV_P2SB _PCH_DEV(LPC, 1) +#define PCH_DEV_PMC _PCH_DEV(LPC, 2) #define PCH_DEV_SMBUS _PCH_DEV(LPC, 4) +#define PCH_DEV_SPI _PCH_DEV(LPC, 5) /* VT-d support value to match FSP settings */ /* "PCH IOAPIC Config" */ diff --git a/src/soc/intel/denverton_ns/include/soc/pm.h b/src/soc/intel/denverton_ns/include/soc/pm.h index 6fc9d90dda..2dc40a5e6c 100644 --- a/src/soc/intel/denverton_ns/include/soc/pm.h +++ b/src/soc/intel/denverton_ns/include/soc/pm.h @@ -45,4 +45,7 @@ void enable_gpe(uint32_t mask); void disable_gpe(uint32_t mask); void disable_all_gpe(void); +/* Clear PMCON status bits */ +void pmc_clear_pmcon_sts(void); + #endif /* _DENVERTON_NS_PM_H_ */ diff --git a/src/soc/intel/denverton_ns/include/soc/pmc.h b/src/soc/intel/denverton_ns/include/soc/pmc.h index 0ba24fcb2f..d5d69cb1a1 100644 --- a/src/soc/intel/denverton_ns/include/soc/pmc.h +++ b/src/soc/intel/denverton_ns/include/soc/pmc.h @@ -3,9 +3,6 @@ #ifndef _DENVERTON_NS_PMC_H_ #define _DENVERTON_NS_PMC_H_ -/* PCI Configuration Space (D31:F2): PMC/ACPI */ -#define PCH_PMC_DEV PCI_DEV(0, PMC_DEV, PMC_FUNC) - /* Memory mapped IO registers behind PMC_BASE_ADDRESS */ #define PMC_ACPI_BASE 0x40 /* IO BAR */ #define MASK_PMC_ACPI_BASE 0xfffc @@ -36,14 +33,15 @@ #define PMC_PWRM_BASE 0x48 /* MEM BAR */ #define MASK_PMC_PWRM_BASE 0xfffff000 /* 4K alignment */ -#define PMC_GEN_PMCON_A 0xA0 -#define PMC_GEN_PMCON_B 0xA4 -#define PMC_GEN_PMCON_B_RTC_PWR_STS 0x04 -#define PMC_GEN_PMCON_B_PWR_FLR 0x02 -#define PMC_GEN_PMCON_B_AFTERG3_EN 0x00 -#define PMC_ETR3 0xAC -#define PMC_ETR3_CF9LOCK BIT31 ///< CF9h Lockdown -#define PMC_ETR3_CF9GR BIT20 ///< CF9h Global Reset +#define GEN_PMCON_A 0xA0 +#define MS4V (1 << 18) +#define GEN_PMCON_B 0xA4 +#define GEN_PMCON_B_RTC_PWR_STS 0x04 +#define GEN_PMCON_B_PWR_FLR 0x02 +#define GEN_PMCON_B_AFTERG3_EN 0x00 +#define ETR3 0xAC +#define ETR3_CF9LOCK BIT31 ///< CF9h Lockdown +#define ETR3_CF9GR BIT20 ///< CF9h Global Reset /* IO Mapped registers behind ACPI_BASE_ADDRESS */ #define PM1_STS 0x00 |