diff options
| author | Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> | 2020-06-18 15:56:11 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-28 21:47:52 +0000 |
| commit | 360684b41aec795d254dcaac1cefb4acf9e129d3 (patch) | |
| tree | c5bbde89d9734c08e7fea993e0403ee05f570091 /src/soc/intel/denverton_ns/include | |
| parent | 5270ce133e068fd35a985b62a22ca64ca2fa9696 (diff) | |
soc/intel/common: add TCC activation functionality
This enables to configure the Thermal Control Circuit (TCC) activation
value to new value as tcc_offset in degree Celcius. It prevents any
abrupt thermal shutdown while running heavy workload. This helps to
take early thermal throttling action before CPU temperature reaches
maximum operating temperature TjMax value. Also, cleanup local functions
from previous intel soc specific code base like for apollolake, broadwell,
skylake and cannonlake.
BUG=None
BRANCH=None
TEST=Built for volteer platform and verified the MSR value.
Change-Id: I37dd878902b080602d70c5c3c906820613ea14a5
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/denverton_ns/include')
| -rw-r--r-- | src/soc/intel/denverton_ns/include/soc/soc_chip.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/denverton_ns/include/soc/soc_chip.h b/src/soc/intel/denverton_ns/include/soc/soc_chip.h new file mode 100644 index 0000000000..800e78e7d1 --- /dev/null +++ b/src/soc/intel/denverton_ns/include/soc/soc_chip.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_DENVERTON_NS_SOC_CHIP_H_ +#define _SOC_DENVERTON_NS_SOC_CHIP_H_ + +#include "../../chip.h" + +#endif /* _SOC_DENVERTON_NS_SOC_CHIP_H_ */ |