diff options
| author | Julien Viard de Galbert <jviarddegalbert@online.net> | 2018-08-14 16:15:26 +0200 |
|---|---|---|
| committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2018-09-14 14:11:03 +0000 |
| commit | 2912e8e5dc66708703db79df87e3215408a653ae (patch) | |
| tree | ce3fd68f9114c4654957e4810f273625a148442f /src/soc/intel/denverton_ns/acpi.c | |
| parent | 86b8d176e8b2d62c1d4a713f91b5858b5d39dd84 (diff) | |
soc/intel/denverton_ns: Enable common block PMC
Mainly update headers to build.
Added option PMC_GLOBAL_RESET_ENABLE_LOCK to remove
function configuring the global reset through PMC base.
On denverton the global reset lock is not in PMC base
but in the PCI registers so this code cannot be shared.
Change-Id: I9ace70862cab63f8355252d034292596c7eab1fd
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/25426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Evandro Luiz Hauenstein <kingsumos@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Diffstat (limited to 'src/soc/intel/denverton_ns/acpi.c')
| -rw-r--r-- | src/soc/intel/denverton_ns/acpi.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 07278c525b..6a947ff83f 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -130,7 +130,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) fadt->pm1b_cnt_blk = 0x0; fadt->pm2_cnt_blk = pmbase + PM2_CNT; fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->gpe0_blk = pmbase + GPE0_STS; + fadt->gpe0_blk = pmbase + GPE0_STS(GPE_STD); fadt->gpe1_blk = 0; /* Control Registers - Length */ |