From 2912e8e5dc66708703db79df87e3215408a653ae Mon Sep 17 00:00:00 2001 From: Julien Viard de Galbert Date: Tue, 14 Aug 2018 16:15:26 +0200 Subject: soc/intel/denverton_ns: Enable common block PMC Mainly update headers to build. Added option PMC_GLOBAL_RESET_ENABLE_LOCK to remove function configuring the global reset through PMC base. On denverton the global reset lock is not in PMC base but in the PCI registers so this code cannot be shared. Change-Id: I9ace70862cab63f8355252d034292596c7eab1fd Signed-off-by: Julien Viard de Galbert Reviewed-on: https://review.coreboot.org/25426 Tested-by: build bot (Jenkins) Reviewed-by: Lijian Zhao Reviewed-by: Evandro Luiz Hauenstein Reviewed-by: Philipp Deppenwiese --- src/soc/intel/denverton_ns/acpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/denverton_ns/acpi.c') diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 07278c525b..6a947ff83f 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -130,7 +130,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) fadt->pm1b_cnt_blk = 0x0; fadt->pm2_cnt_blk = pmbase + PM2_CNT; fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->gpe0_blk = pmbase + GPE0_STS; + fadt->gpe0_blk = pmbase + GPE0_STS(GPE_STD); fadt->gpe1_blk = 0; /* Control Registers - Length */ -- cgit v1.2.3