diff options
| author | Julien Viard de Galbert <jviarddegalbert@online.net> | 2018-03-29 11:36:21 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-05-14 21:03:17 +0000 |
| commit | 3ac3a68eef7ebd14cee7e09e22f02a8f6ce54f24 (patch) | |
| tree | 97de336fd9e5a83956802cfdec0afae336382c34 /src/soc/intel/denverton_ns/Kconfig | |
| parent | 7ebb6b0f00ed6b8f92749cc4b035f02c001197e7 (diff) | |
soc/intel/denverton_ns: port gpio to intelblock
The intelblock code is common code already used by appololake and
cannonlake platform. The denverton platform also use a similar gpio
controller so the intelblock code can be used as well.
Change-Id: I7ecfb5a3527e9c893930149f7b847a41c5dd9374
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/24928
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/denverton_ns/Kconfig')
| -rw-r--r-- | src/soc/intel/denverton_ns/Kconfig | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 8d9a55002f..d666bcc88c 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -42,10 +42,14 @@ config CPU_SPECIFIC_OPTIONS select CACHE_MRC_SETTINGS select RELOCATABLE_RAMSTAGE # Build fails if this is not selected select PARALLEL_MP + select PCR_COMMON_IOSF_1_0 select SMP select SOC_INTEL_COMMON_BLOCK # select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_FAST_SPI + select SOC_INTEL_COMMON_BLOCK_GPIO + select DEBUG_SOC_COMMON_BLOCK_GPIO + select SOC_INTEL_COMMON_BLOCK_PCR select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE @@ -86,6 +90,12 @@ config MAX_CPUS int default 16 +config PCR_BASE_ADDRESS + hex + default 0xfd000000 + help + This option allows you to select MMIO Base Address of sideband bus. + config DCACHE_RAM_BASE hex default 0xfef00000 |