From 3ac3a68eef7ebd14cee7e09e22f02a8f6ce54f24 Mon Sep 17 00:00:00 2001 From: Julien Viard de Galbert Date: Thu, 29 Mar 2018 11:36:21 +0200 Subject: soc/intel/denverton_ns: port gpio to intelblock The intelblock code is common code already used by appololake and cannonlake platform. The denverton platform also use a similar gpio controller so the intelblock code can be used as well. Change-Id: I7ecfb5a3527e9c893930149f7b847a41c5dd9374 Signed-off-by: Julien Viard de Galbert Reviewed-on: https://review.coreboot.org/24928 Reviewed-by: Philipp Deppenwiese Tested-by: build bot (Jenkins) --- src/soc/intel/denverton_ns/Kconfig | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src/soc/intel/denverton_ns/Kconfig') diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 8d9a55002f..d666bcc88c 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -42,10 +42,14 @@ config CPU_SPECIFIC_OPTIONS select CACHE_MRC_SETTINGS select RELOCATABLE_RAMSTAGE # Build fails if this is not selected select PARALLEL_MP + select PCR_COMMON_IOSF_1_0 select SMP select SOC_INTEL_COMMON_BLOCK # select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_FAST_SPI + select SOC_INTEL_COMMON_BLOCK_GPIO + select DEBUG_SOC_COMMON_BLOCK_GPIO + select SOC_INTEL_COMMON_BLOCK_PCR select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE @@ -86,6 +90,12 @@ config MAX_CPUS int default 16 +config PCR_BASE_ADDRESS + hex + default 0xfd000000 + help + This option allows you to select MMIO Base Address of sideband bus. + config DCACHE_RAM_BASE hex default 0xfef00000 -- cgit v1.2.3