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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2023-06-30 18:44:26 +0300 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-07-06 13:54:20 +0000 |
| commit | a52b93b262582009decf924dbdde9bc1bf856ddb (patch) | |
| tree | c1bb9a7ef4c8abe5d82381f6c160741a620ab33a /src/soc/intel/common | |
| parent | 053a45bcdb3ccf8a686b35c97e8404c386f65d58 (diff) | |
cpu/x86: Add some notes about XAPIC/X2APIC
At the time of writing SMM runtime does not make register
accesses to LAPIC registers, but such breakage has been
reported.
S3 resume failure, where OS switched back from X2APIC
to XAPIC mode, can be reproduced with a sandybridge SKU
that has VT-d disabled.
Change-Id: I300ba87c3d8fde548dbaf95703bd7e2fe54cff57
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Diffstat (limited to 'src/soc/intel/common')
0 files changed, 0 insertions, 0 deletions