diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-25 09:56:20 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-06-22 13:14:53 +0000 |
| commit | 99a48bc824d6524a780a987e8e22cf22bdb9eae1 (patch) | |
| tree | b530e25498a8420e1c5f412a07c50957e9d405bf /src/soc/intel/common | |
| parent | 64c9c6d54c2bfc4b3d7c9058f2a80a56b58a9a4f (diff) | |
soc/intel/common/cache_as_ram.S: Add macro to clear CAR
Add a macro to clear CAR which is replicated 3 times in this code.
TEST: with BUILD_TIMELESS=1 the resulting binary is identical.
Change-Id: Iec28e3f393c4fe222bfb0d5358f815691ec199ae
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/cpu/car/cache_as_ram.S | 42 |
1 files changed, 22 insertions, 20 deletions
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index db1345ac42..5da453b527 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -41,6 +41,23 @@ decl %ecx .endm +/* + * macro: clear_car + * Clears the region between CONFIG_DCACHE_RAM_BASE and + * CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE to populate + * cachelines. + * Clobbers %eax, %ecx, %edi. + */ +.macro clear_car + /* Clear the cache memory region. This will also fill up the cache */ + movl $CONFIG_DCACHE_RAM_BASE, %edi + movl $CONFIG_DCACHE_RAM_SIZE, %ecx + shr $0x02, %ecx + xor %eax, %eax + cld + rep stosl +.endm + .global bootblock_pre_c_entry bootblock_pre_c_entry: @@ -256,13 +273,7 @@ car_nem: post_code(0x26) - /* Clear the cache memory region. This will also fill up the cache */ - movl $CONFIG_DCACHE_RAM_BASE, %edi - movl $CONFIG_DCACHE_RAM_SIZE, %ecx - shr $0x02, %ecx - xor %eax, %eax - cld - rep stosl + clear_car post_code(0x27) @@ -353,13 +364,7 @@ car_cqos: post_code(0x26) - /* Clear the cache memory region. This will also fill up the cache */ - movl $CONFIG_DCACHE_RAM_BASE, %edi - movl $CONFIG_DCACHE_RAM_SIZE, %ecx - shr $0x02, %ecx - xor %eax, %eax - cld - rep stosl + clear_car post_code(0x27) @@ -518,12 +523,9 @@ set_eviction_mask: movl $0x02, %eax #endif wrmsr - movl $CONFIG_DCACHE_RAM_BASE, %edi - movl $CONFIG_DCACHE_RAM_SIZE, %ecx - shr $0x02, %ecx - xor %eax, %eax - cld - rep stosl + + clear_car + /* * Set IA32_PQR_ASSOC * At this stage we apply LLC_WAY_MASK_1 to the cache. |