diff options
author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-06-25 22:44:45 -0600 |
---|---|---|
committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-09-10 19:39:42 +0000 |
commit | 64246480a656b2eba8a895a962787051ee2d4378 (patch) | |
tree | 6390d95b4a229eadfc0fe9c39edca1ac329429a3 /src/soc/intel/common | |
parent | d96f3a25b43aaa999fab5a905f027bc29e5d2d47 (diff) |
soc/intel/common/block/acpi: Move pep.asl to acpigen
There is a use-case for generating the AML bytecode at runtime for the
Intel Power Engine device, which comes in a followup patch.
BUG=b:185437326
TEST=verified on google/brya and google/dratini by dumping SSDT and
verifying the PEPD device matches what was previously in the DSDT:
Scope (\_SB.PCI0)
{
Device (PEPD)
{
Name (_HID, "INT33A1")
Name (_CID, EisaId ("PNP0D80")
Method (_DSM, 4, Serialized)
{
ToBuffer (Arg0, Local0)
If ((Local0 == ToUUID ("c4eb40a0-6cd2-11e2-bcfd-0800200c9a66")))
{
ToInteger (Arg2, Local1)
If ((Local1 == Zero))
{
Return (Buffer (One)
{
0x63
})
}
If ((Local1 == One))
{
Return (Package (0x01)
{
Package (0x03)
{
\NULL,
Zero,
Package (0x02)
{
Zero,
Package (0x02)
{
0xFF,
Zero
}
}
}
})
}
If ((Local1 == 0x02)){}
If ((Local1 == 0x03)){}
If ((Local1 == 0x04)){}
If ((Local1 == 0x05))
{
If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX))
{
\_SB.PCI0.LPCB.EC0.S0IX (One)
}
If (CondRefOf (\_SB.MS0X))
{
\_SB.MS0X (One)
}
If (CondRefOf (\_SB.PCI0.EGPM))
{
\_SB.PCI0.EGPM ()
}
}
If ((Local1 == 0x06))
{
If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX))
{
\_SB.PCI0.LPCB.EC0.S0IX (Zero)
}
If (CondRefOf (\_SB.MS0X))
{
\_SB.MS0X (Zero)
}
If (CondRefOf (\_SB.PCI0.RGPM))
{
\_SB.PCI0.RGPM ()
}
}
Return (Buffer (One)
{
0x00
})
}
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie83722e0ed5792e338fc5c39a57eef43b7464e3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/common')
-rw-r--r-- | src/soc/intel/common/block/acpi/Kconfig | 8 | ||||
-rw-r--r-- | src/soc/intel/common/block/acpi/Makefile.inc | 1 | ||||
-rw-r--r-- | src/soc/intel/common/block/acpi/pep.c | 122 | ||||
-rw-r--r-- | src/soc/intel/common/block/include/intelblocks/acpi.h | 3 |
4 files changed, 133 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/acpi/Kconfig b/src/soc/intel/common/block/acpi/Kconfig index 6aa3abcad9..cc4cd71fdc 100644 --- a/src/soc/intel/common/block/acpi/Kconfig +++ b/src/soc/intel/common/block/acpi/Kconfig @@ -15,6 +15,13 @@ config SOC_INTEL_COMMON_BLOCK_ACPI_LPIT help Generate LPIT table with LPI state entries +config SOC_INTEL_COMMON_BLOCK_ACPI_PEP + bool + depends on HAVE_ACPI_TABLES + help + Generate an Intel Power Engine device object in the SSDT. This is + usually used for providing ACPI hooks for S0ix exit/entry. + config SOC_INTEL_COMMON_BLOCK_CRASHLOG bool depends on SOC_INTEL_CRASHLOG @@ -28,5 +35,4 @@ config SOC_INTEL_COMMON_BLOCK_ACPI_CPPC help Generate CPPC entries for Intel SpeedShift - endif diff --git a/src/soc/intel/common/block/acpi/Makefile.inc b/src/soc/intel/common/block/acpi/Makefile.inc index c78dbc0d84..c8eaad5c25 100644 --- a/src/soc/intel/common/block/acpi/Makefile.inc +++ b/src/soc/intel/common/block/acpi/Makefile.inc @@ -3,3 +3,4 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPIO) += gpio.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_LPIT) += lpit.c ramstage-$(CONFIG_ACPI_BERT) += acpi_bert.c ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_PEP) += pep.c diff --git a/src/soc/intel/common/block/acpi/pep.c b/src/soc/intel/common/block/acpi/pep.c new file mode 100644 index 0000000000..9b15bf3b32 --- /dev/null +++ b/src/soc/intel/common/block/acpi/pep.c @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpigen.h> +#include <console/console.h> +#include <intelblocks/acpi.h> +#include <types.h> + +#define LPI_S0_HELPER_UUID "c4eb40a0-6cd2-11e2-bcfd-0800200c9a66" +#define SYSTEM_POWER_MANAGEMENT_HID "INT33A1" +#define SYSTEM_POWER_MANAGEMENT_CID "PNP0D80" +#define EC_S0IX_HOOK "\\_SB.PCI0.LPCB.EC0.S0IX" +#define MAINBOARD_HOOK "\\_SB.MS0X" +#define ENABLE_PM_BITS_HOOK "\\_SB.PCI0.EGPM" +#define RESTORE_PM_BITS_HOOK "\\_SB.PCI0.RGPM" +#define LPI_STATES_ALL 0xff +#define MIN_DEVICE_STATE ACPI_DEVICE_SLEEP_D0 +#define PEPD_SCOPE "\\_SB.PCI0" + +/* + * For now there is only one disabled non-existent device, because Windows + * expects at least one device and crashes without it with a bluescreen + * (`INTERNAL_POWER_ERROR`). Returning an empty package does not work. + */ +static void lpi_get_constraints(void *unused) +{ + /* + * Return (Package() { + * Package() { "\NULL", 0, + * Package() { 0, + * Package() { 0xff, 0 }}}}) + */ + acpigen_emit_byte(RETURN_OP); + acpigen_write_package(1); + { + acpigen_write_package(3); + { + acpigen_emit_namestring("\\NULL"); + acpigen_write_integer(0); /* device disabled */ + acpigen_write_package(2); + { + acpigen_write_integer(0); /* revision */ + acpigen_write_package(2); + { + acpigen_write_integer(LPI_STATES_ALL); + acpigen_write_integer(MIN_DEVICE_STATE); + } + acpigen_write_package_end(); + } + acpigen_write_package_end(); + } + acpigen_write_package_end(); + } + acpigen_write_package_end(); +} + +static void lpi_s0ix_entry(void *unused) +{ + /* Inform the EC */ + acpigen_write_if_cond_ref_of(EC_S0IX_HOOK); + acpigen_emit_namestring(EC_S0IX_HOOK); + acpigen_write_integer(1); + acpigen_write_if_end(); + + /* Provide a board level S0ix hook */ + acpigen_write_if_cond_ref_of(MAINBOARD_HOOK); + acpigen_emit_namestring(MAINBOARD_HOOK); + acpigen_write_integer(1); + acpigen_write_if_end(); + + /* Save the current PM bits then enable GPIO PM with + MISCCFG_GPIO_PM_CONFIG_BITS */ + acpigen_write_if_cond_ref_of(ENABLE_PM_BITS_HOOK); + acpigen_emit_namestring(ENABLE_PM_BITS_HOOK); + acpigen_write_if_end(); +} + +static void lpi_s0ix_exit(void *unused) +{ + /* Inform the EC */ + acpigen_write_if_cond_ref_of(EC_S0IX_HOOK); + acpigen_emit_namestring(EC_S0IX_HOOK); + acpigen_write_integer(0); + acpigen_write_if_end(); + + /* Provide a board level S0ix hook */ + acpigen_write_if_cond_ref_of(MAINBOARD_HOOK); + acpigen_emit_namestring(MAINBOARD_HOOK); + acpigen_write_integer(0); + acpigen_write_if_end(); + + /* Restore GPIO all Community PM */ + acpigen_write_if_cond_ref_of(RESTORE_PM_BITS_HOOK); + acpigen_emit_namestring(RESTORE_PM_BITS_HOOK); + acpigen_write_if_end(); +} + +static void (*lpi_s0_helpers[])(void *) = { + NULL, /* enumerate functions (autogenerated) */ + lpi_get_constraints, /* get device constraints */ + NULL, /* get crash dump device */ + NULL, /* display off notify */ + NULL, /* display on notify */ + lpi_s0ix_entry, /* s0ix entry */ + lpi_s0ix_exit, /* s0ix exit */ +}; + +void generate_acpi_power_engine(void) +{ + acpigen_write_scope(PEPD_SCOPE); + acpigen_write_device("PEPD"); + + acpigen_write_name_string("_HID", SYSTEM_POWER_MANAGEMENT_HID); + acpigen_write_name("_CID"); + acpigen_emit_eisaid(SYSTEM_POWER_MANAGEMENT_CID); + + acpigen_write_dsm(LPI_S0_HELPER_UUID, lpi_s0_helpers, ARRAY_SIZE(lpi_s0_helpers), NULL); + + acpigen_write_device_end(); + acpigen_write_scope_end(); + + printk(BIOS_INFO, PEPD_SCOPE ".PEPD: Intel Power Engine Plug-in\n"); +} diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index 90d5e5e522..5eb1a9bf48 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -90,4 +90,7 @@ struct madt_ioapic_info { */ const struct madt_ioapic_info *soc_get_ioapic_info(size_t *entries); +/* Generate an Intel Power Engine ACPI device */ +void generate_acpi_power_engine(void); + #endif /* _SOC_INTEL_COMMON_BLOCK_ACPI_H_ */ |