diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-04-14 13:48:53 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-04-23 17:16:15 +0000 |
| commit | 4c6072130c0979095a6639af4c5c06937f785145 (patch) | |
| tree | 67783eed8d484767c39f54aceaf8d97226783c71 /src/soc/intel/common | |
| parent | fa2854d3dc6d5a56f465e6aef4621503ca5f5e34 (diff) | |
soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration
This patch implements a helper function to perform LPC registers lock
down configuration.
BUG=b:211954778
TEST=Able to build and boot google/redrix to OS. Verified LPC PCI
configuration register offset 0xDC bits BILD and LE are set.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3e49b783e5db0ff40238e6e9259e48a4ecca66f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/pch/lockdown/lockdown.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index 8032b4ac3e..cd8b402b5d 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -3,6 +3,7 @@ #include <bootstate.h> #include <intelblocks/cfg.h> #include <intelblocks/fast_spi.h> +#include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> #include <intelpch/lockdown.h> #include <intelblocks/gpmr.h> @@ -88,6 +89,24 @@ static void fast_spi_lockdown_cfg(int chipset_lockdown) } } +static void lpc_lockdown_config(int chipset_lockdown) +{ + /* Set BIOS Interface Lock, BIOS Lock */ + if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { + /* BIOS Interface Lock */ + lpc_set_bios_interface_lock_down(); + + /* Only allow writes in SMM */ + if (CONFIG(BOOTMEDIA_SMM_BWP)) { + lpc_set_eiss(); + lpc_enable_wp(); + } + + /* BIOS Lock */ + lpc_set_lock_enable(); + } +} + /* * platform_lockdown_config has 2 major part. * 1. Common SoC lockdown configuration. @@ -102,6 +121,9 @@ static void platform_lockdown_config(void *unused) /* SPI lock down configuration */ fast_spi_lockdown_cfg(chipset_lockdown); + /* LPC/eSPI lock down configuration */ + lpc_lockdown_config(chipset_lockdown); + /* DMI lock down configuration */ lockdown_cfg(); |