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authorDuncan Laurie <dlaurie@google.com>2018-10-29 16:48:02 -0700
committerDuncan Laurie <dlaurie@chromium.org>2018-11-02 16:06:53 +0000
commitf95b4a708e021f4eb3cb36aa1f3bc6a2076f2f6b (patch)
treeb3b57e453814c58c71fea1dfeb8130158cfad7d5 /src/soc/intel/common
parent51f2f2eba1778167e9d281b8c7a7c9b9792a37cb (diff)
soc/intel: Enable GPIO functions in verstage
Enable GPIO functionality in verstage so platforms can read a PCH GPIO in verstage to determine recovery mode. Change-Id: Icd4344c4d66dbe21fda9dc27e61a836c1dd9be07 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29407 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common')
-rw-r--r--src/soc/intel/common/block/gpio/Makefile.inc1
-rw-r--r--src/soc/intel/common/block/pcr/Makefile.inc1
2 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/gpio/Makefile.inc b/src/soc/intel/common/block/gpio/Makefile.inc
index bf40397b26..b0ffee308a 100644
--- a/src/soc/intel/common/block/gpio/Makefile.inc
+++ b/src/soc/intel/common/block/gpio/Makefile.inc
@@ -2,3 +2,4 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c
romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c
smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c
+verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c
diff --git a/src/soc/intel/common/block/pcr/Makefile.inc b/src/soc/intel/common/block/pcr/Makefile.inc
index c64fe7a57a..0577e0ac4f 100644
--- a/src/soc/intel/common/block/pcr/Makefile.inc
+++ b/src/soc/intel/common/block/pcr/Makefile.inc
@@ -2,3 +2,4 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c
romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c
smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c
+verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c