From f95b4a708e021f4eb3cb36aa1f3bc6a2076f2f6b Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Mon, 29 Oct 2018 16:48:02 -0700 Subject: soc/intel: Enable GPIO functions in verstage Enable GPIO functionality in verstage so platforms can read a PCH GPIO in verstage to determine recovery mode. Change-Id: Icd4344c4d66dbe21fda9dc27e61a836c1dd9be07 Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/29407 Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/gpio/Makefile.inc | 1 + src/soc/intel/common/block/pcr/Makefile.inc | 1 + 2 files changed, 2 insertions(+) (limited to 'src/soc/intel/common') diff --git a/src/soc/intel/common/block/gpio/Makefile.inc b/src/soc/intel/common/block/gpio/Makefile.inc index bf40397b26..b0ffee308a 100644 --- a/src/soc/intel/common/block/gpio/Makefile.inc +++ b/src/soc/intel/common/block/gpio/Makefile.inc @@ -2,3 +2,4 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c +verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c diff --git a/src/soc/intel/common/block/pcr/Makefile.inc b/src/soc/intel/common/block/pcr/Makefile.inc index c64fe7a57a..0577e0ac4f 100644 --- a/src/soc/intel/common/block/pcr/Makefile.inc +++ b/src/soc/intel/common/block/pcr/Makefile.inc @@ -2,3 +2,4 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c +verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c -- cgit v1.2.3