diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-07-24 08:03:37 -0700 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2016-07-27 13:50:11 +0200 |
| commit | ae738acdc5f02d232e035538c67d63ba19b9ccaa (patch) | |
| tree | 862a877545dad919c698b48381a115bd15130fcc /src/soc/intel/common/util.c | |
| parent | 7c2e5396a3d47c64eb5a553fe412aad4c0f8dc1b (diff) | |
cpu/x86: Support CPUs without rdmsr/wrmsr instructions
Quark does not support the rdmsr and wrmsr instructions. In this case
use a SOC specific routine to support the setting of the MTRRs. Migrate
the code from FSP 1.1 to be x86 CPU common.
Since all rdmsr/wrmsr accesses are being converted, fix the build
failure for quark in lib/reg_script.c. Move the soc_msr_x routines and
their depencies from romstage/mtrr.c to reg_access.c.
TEST=Build and run on Galileo Gen2
Change-Id: Ibc68e696d8066fbe2322f446d8c983d3f86052ea
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15839
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common/util.c')
| -rw-r--r-- | src/soc/intel/common/util.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/soc/intel/common/util.c b/src/soc/intel/common/util.c index 74ce9ff28f..2d3a34a63a 100644 --- a/src/soc/intel/common/util.c +++ b/src/soc/intel/common/util.c @@ -26,7 +26,7 @@ uint32_t soc_get_variable_mtrr_count(uint64_t *msr) msr_t s; } mtrrcap; - mtrrcap.s = soc_mtrr_read(MTRR_CAP_MSR); + mtrrcap.s = rdmsr(MTRR_CAP_MSR); if (msr != NULL) *msr = mtrrcap.u64; return mtrrcap.u64 & MTRR_CAP_VCNT; @@ -83,7 +83,7 @@ static void soc_display_4k_mtrr(uint32_t msr_reg, uint32_t starting_address, msr_t s; } msr; - msr.s = soc_mtrr_read(msr_reg); + msr.s = rdmsr(msr_reg); printk(BIOS_DEBUG, "0x%016llx: %s\n", msr.u64, name); soc_display_mtrr_fixed_types(msr.u64, starting_address, 0x1000); } @@ -96,7 +96,7 @@ static void soc_display_16k_mtrr(uint32_t msr_reg, uint32_t starting_address, msr_t s; } msr; - msr.s = soc_mtrr_read(msr_reg); + msr.s = rdmsr(msr_reg); printk(BIOS_DEBUG, "0x%016llx: %s\n", msr.u64, name); soc_display_mtrr_fixed_types(msr.u64, starting_address, 0x4000); } @@ -108,7 +108,7 @@ static void soc_display_64k_mtrr(void) msr_t s; } msr; - msr.s = soc_mtrr_read(MTRR_FIX_64K_00000); + msr.s = rdmsr(MTRR_FIX_64K_00000); printk(BIOS_DEBUG, "0x%016llx: IA32_MTRR_FIX64K_00000\n", msr.u64); soc_display_mtrr_fixed_types(msr.u64, 0, 0x10000); } @@ -136,7 +136,7 @@ static void soc_display_mtrr_def_type(void) msr_t s; } msr; - msr.s = soc_mtrr_read(MTRR_DEF_TYPE_MSR); + msr.s = rdmsr(MTRR_DEF_TYPE_MSR); printk(BIOS_DEBUG, "0x%016llx: IA32_MTRR_DEF_TYPE:%s%s %s\n", msr.u64, (msr.u64 & MTRR_DEF_TYPE_EN) ? " E," : "", @@ -160,8 +160,8 @@ static void soc_display_variable_mtrr(uint32_t msr_reg, int index, msr_t s; } msr_m; - msr_a.s = soc_mtrr_read(msr_reg); - msr_m.s = soc_mtrr_read(msr_reg + 1); + msr_a.s = rdmsr(msr_reg); + msr_m.s = rdmsr(msr_reg + 1); if (msr_m.u64 & MTRR_PHYS_MASK_VALID) { base_address = (msr_a.u64 & 0xfffffffffffff000ULL) & address_mask; |