diff options
| author | Shuo Liu <shuo.liu@intel.com> | 2024-03-11 04:56:19 +0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-04-01 08:04:34 +0000 |
| commit | 96d7524ee69f07cc54ecf5527953380c8c5f5c48 (patch) | |
| tree | a2886987329ceb1989855cd47985891fecc0a267 /src/soc/intel/common/pch/Kconfig | |
| parent | f2daf2480b8f387bc4e44cb2b4c573da0a8e1b44 (diff) | |
intel/common/pch: Add Kconfig SOC_INTEL_COMMON_IBL_BASE
IBL (Integrated Boot Logic) provides a subset of server
PCH logics for no-PCH solution. IBL is with limited features
and registers exposed, PCIe root ports/USB/SATA/LAN support are
removed.
Change-Id: I8f3d64a2dd3b79ec5a9e4306f40b012b00387259
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81314
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/pch/Kconfig')
| -rw-r--r-- | src/soc/intel/common/pch/Kconfig | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig index 716a786e68..32902aa9f1 100644 --- a/src/soc/intel/common/pch/Kconfig +++ b/src/soc/intel/common/pch/Kconfig @@ -75,3 +75,36 @@ config PCH_SPECIFIC_CLIENT_OPTIONS select SOC_INTEL_COMMON_BLOCK_XDCI endif # SOC_INTEL_COMMON_PCH_BASE + +config SOC_INTEL_COMMON_IBL_BASE + bool + depends on SOC_INTEL_COMMON_BLOCK + depends on !SOC_INTEL_COMMON_PCH_BASE + help + Common code blocks for integrated boot logic known as IBL. IBL is still + compatible with PCH interfaces, but with limited features/registers + exposed and certain revises. + +if SOC_INTEL_COMMON_IBL_BASE + +source "src/soc/intel/common/pch/*/Kconfig" + +config IBL_SPECIFIC_BASE_OPTIONS + def_bool y + select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG + select SOC_INTEL_COMMON_BLOCK_FAST_SPI + select SOC_INTEL_COMMON_BLOCK_GPIO + select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG + select SOC_INTEL_COMMON_BLOCK_ITSS + select SOC_INTEL_COMMON_BLOCK_LPC + select SOC_INTEL_COMMON_BLOCK_P2SB + select SOC_INTEL_COMMON_BLOCK_PCR + select SOC_INTEL_COMMON_BLOCK_PMC + select SOC_INTEL_COMMON_BLOCK_RTC + select SOC_INTEL_COMMON_BLOCK_SMBUS + select SOC_INTEL_COMMON_BLOCK_SPI + select SOC_INTEL_COMMON_BLOCK_TIMER + select SOC_INTEL_COMMON_PCH_LOCKDOWN + select SOUTHBRIDGE_INTEL_COMMON_SMBUS + +endif # SOC_INTEL_COMMON_IBL_BASE |