diff options
| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2021-01-11 16:14:14 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-18 07:28:32 +0000 |
| commit | de2ab41fc43152b652af7c1f658b1c27926afd6c (patch) | |
| tree | 6313677b0de43ae3eb3e601a6fa66e1f8c0e8414 /src/soc/intel/common/block | |
| parent | cb18524b4a789195c78490fea9398178d4d043fe (diff) | |
soc/intel/common: Move L1_substates_control to pcie_rp.h
L1_substates_control is common define. Move out of soc level.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I54574b606985e82d00beb1a61cce3097580366a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/common/block')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/pcie_rp.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h index 578a600e5b..2030e72453 100644 --- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h +++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h @@ -63,4 +63,12 @@ void pcie_rp_update_devicetree(const struct pcie_rp_group *groups); */ uint32_t pcie_rp_enable_mask(const struct pcie_rp_group *groups); +/* This enum is for passing into an FSP UPD, typically PcieRpL1Substates */ +enum L1_substates_control { + L1_SS_FSP_DEFAULT, + L1_SS_DISABLED, + L1_SS_L1_1, + L1_SS_L1_2, +}; + #endif /* SOC_INTEL_COMMON_BLOCK_PCIE_RP_H */ |