diff options
| author | Subrata Banik <subratabanik@google.com> | 2024-09-02 17:04:14 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-09-04 12:54:55 +0000 |
| commit | 8db1dfb9cb8ae797214f7506a3204faf3af00945 (patch) | |
| tree | 62c80abfd2e8d0020f94dabeadcc594e3e68b75a /src/soc/intel/common/block | |
| parent | 13cee3c19599b8f4acdb9a9fc5ad78716cc70d6d (diff) | |
soc/intel: Refactor ITSS macros
This patch refactors ITSS related SoC specific macros by consolidating
them into a common itss.h file. This improves code maintainability and
reduces redundancy as each SoC previously defined the same macros.
Specific changes include:
- Move SoC specific ITSS macros into intelblocks/itss.h.
- SoC code now includes intelblocks/itss.h instead of the SoC-local
soc/itss.h.
- Drop soc/itss.h from static ASL files.
- Delete soc/itss.h from all SoC locals except Apollo Lake and
Sky Lake.
TEST=Able to build and boot google/hatch, google/xol and google/karis.
Change-Id: I6461dc93b0d21bec5429075bc26435bae3754d74
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84183
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Diffstat (limited to 'src/soc/intel/common/block')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/itss.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/common/block/itss/itss.c | 1 |
2 files changed, 4 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/itss.h b/src/soc/intel/common/block/include/intelblocks/itss.h index 4d26b25b4d..84ba7b443a 100644 --- a/src/soc/intel/common/block/include/intelblocks/itss.h +++ b/src/soc/intel/common/block/include/intelblocks/itss.h @@ -3,6 +3,10 @@ #ifndef SOC_INTEL_COMMON_BLOCK_ITSS_H #define SOC_INTEL_COMMON_BLOCK_ITSS_H +#define ITSS_MAX_IRQ 119 +#define IRQS_PER_IPC 32 +#define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC) + /* PIRQA Routing Control Register */ #define PCR_ITSS_PIRQA_ROUT 0x3100 /* PIRQB Routing Control Register */ diff --git a/src/soc/intel/common/block/itss/itss.c b/src/soc/intel/common/block/itss/itss.c index 79ed5d0572..50e4c38790 100644 --- a/src/soc/intel/common/block/itss/itss.c +++ b/src/soc/intel/common/block/itss/itss.c @@ -5,7 +5,6 @@ #include <console/console.h> #include <intelblocks/itss.h> #include <intelblocks/pcr.h> -#include <soc/itss.h> #include <soc/pcr_ids.h> #include <southbridge/intel/common/acpi_pirq_gen.h> |