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| author | Van Chen <van_chen@compal.corp-partner.google.com> | 2023-07-24 15:14:16 +0800 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-08-05 16:03:04 +0000 |
| commit | 8c77e58cd6a8caaf0c75916391d04e43e1a11aa9 (patch) | |
| tree | 5ec19578691388eee26fcf3dbdfe31a95eca6ec0 /src/soc/intel/common/block | |
| parent | 5a53c4ddafc47d9972c1d2724d3f922eb05ea5bc (diff) | |
mb/google/nissa/var/craaskov: Add DPTF parameters
The DPTF parameters were verified by the thermal team.
Based on thermal table in 290705146#comment11.
Set "tcc_offset" = "8"
BUG=b:290705146
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I2d9e1ad2e2fa98757d76578956101a482073885e
Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76712
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/soc/intel/common/block')
0 files changed, 0 insertions, 0 deletions