diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-08-16 14:43:03 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-08-30 16:35:10 +0000 |
| commit | 7b42153e589eaabfca590f033e53ed85b313e64a (patch) | |
| tree | 8d815d5ad7fdfb4265149f65bc00c6e8cd239880 /src/soc/intel/common/block | |
| parent | a057d2cfd1b19376a732aba109f0a4b79f4b6936 (diff) | |
soc/intel/cmn/block/acpi: Add new GPIO ASL Method
Ths new Method, GSCI, allows control over whether or not IRQs are routed
as SCI#s for the given GPIO.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ic61caaf77d2c6e295e67a1501544e8b8fc6f3b6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66813
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block')
| -rw-r--r-- | src/soc/intel/common/block/acpi/acpi/gpio_op.asl | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/acpi/acpi/gpio_op.asl b/src/soc/intel/common/block/acpi/acpi/gpio_op.asl index 55d254057a..25e73651b0 100644 --- a/src/soc/intel/common/block/acpi/acpi/gpio_op.asl +++ b/src/soc/intel/common/block/acpi/acpi/gpio_op.asl @@ -117,3 +117,22 @@ Method (GRXE, 2, Serialized) RXDI = !Arg1 } + +/* + * Enable/Disable SCI interrupt route + * Arg0 - GPIO Number + * Arg1 - Route to SCI# + * 0 = Disable IRQ route to SCI# + * 1 = Enable IRQ route to SCI# + */ +Method (GSCI, 2, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + , 19, + SCIR, 1, + } + + SCIR = Arg1 +} |