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authorSubrata Banik <subrata.banik@intel.com>2017-08-29 18:51:14 +0530
committerSubrata Banik <subrata.banik@intel.com>2017-08-30 15:46:08 +0000
commit73f448f04d75eeb5869fc686de33528288285a31 (patch)
tree838ad3394dc20b8ab06cfd56177cc5af4ea34932 /src/soc/intel/common/block
parent2678cd693a766f722e67c7d650a95e1d4a9af404 (diff)
soc/intel/common: Add functions into common system agent library
This patch to add helper function to get tseg memory base and size for HW based memory layout design. BRANCH=none BUG=b:63974384 TEST=Build and boot eve successfully. Change-Id: I4c8b79f047e3dc6b2deb17fdb745f004004526b6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common/block')
-rw-r--r--src/soc/intel/common/block/include/intelblocks/systemagent.h6
-rw-r--r--src/soc/intel/common/block/systemagent/systemagent_early.c19
2 files changed, 23 insertions, 2 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h
index 5f04e3643c..4ca19e667c 100644
--- a/src/soc/intel/common/block/include/intelblocks/systemagent.h
+++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h
@@ -74,11 +74,15 @@ void enable_pam_region(void);
/* API to enable Power Aware Interrupt Routing through MCHBAR */
void enable_power_aware_intr(void);
/* API to get TOLUD base address */
-uint32_t sa_get_tolud_base(void);
+uintptr_t sa_get_tolud_base(void);
/* API to get DSM size */
size_t sa_get_dsm_size(void);
/* API to get GSM size */
size_t sa_get_gsm_size(void);
+/* API to get TSEG base address */
+uintptr_t sa_get_tseg_base(void);
+/* API to get TSEG size */
+size_t sa_get_tseg_size(void);
/* API to get DPR size */
size_t sa_get_dpr_size(void);
/*
diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c
index 855d953b68..4abc15f59a 100644
--- a/src/soc/intel/common/block/systemagent/systemagent_early.c
+++ b/src/soc/intel/common/block/systemagent/systemagent_early.c
@@ -133,7 +133,7 @@ void enable_bios_reset_cpl(void)
MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl;
}
-uint32_t sa_get_tolud_base(void)
+uintptr_t sa_get_tolud_base(void)
{
/* All regions concerned for have 1 MiB alignment. */
return ALIGN_DOWN(pci_read_config32(SA_DEV_ROOT, TOLUD), 1*MiB);
@@ -149,6 +149,12 @@ size_t sa_get_dsm_size(void)
return (((sa_get_ggc_reg() & G_GMS_MASK) >> G_GMS_OFFSET) * 32*MiB);
}
+static uintptr_t sa_get_gsm_base(void)
+{
+ /* All regions concerned for have 1 MiB alignment. */
+ return ALIGN_DOWN(pci_read_config32(SA_DEV_ROOT, BGSM), 1*MiB);
+}
+
size_t sa_get_gsm_size(void)
{
uint8_t ggms;
@@ -165,6 +171,17 @@ size_t sa_get_gsm_size(void)
return 0;
}
+uintptr_t sa_get_tseg_base(void)
+{
+ /* All regions concerned for have 1 MiB alignment. */
+ return ALIGN_DOWN(pci_read_config32(SA_DEV_ROOT, TSEG), 1*MiB);
+}
+
+size_t sa_get_tseg_size(void)
+{
+ return sa_get_gsm_base() - sa_get_tseg_base();
+}
+
/*
* Get DPR size in case CONFIG_SA_ENABLE_DPR is selected by SoC.
*/