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authorlilacious <yuchenhe126@gmail.com>2023-06-21 23:24:14 +0200
committerFelix Held <felix-coreboot@felixheld.de>2023-06-23 15:06:04 +0000
commit40cb3fe94dacfba0b146aae2be9c03c0a0ddb691 (patch)
tree9dc68ba4ab1d8033939e1a872b374fc2ef3ba504 /src/soc/intel/common/block
parentbb4bc777b7b6566cd030f2c4eef4b5e2c8425349 (diff)
commonlib/console/post_code.h: Change post code prefix to POSTCODE
The prefix POSTCODE makes it clear that the macro is a post code. Hence, replace related macros starting with POST to POSTCODE and also replace every instance the macros are invoked with the new name. The files was changed by running the following bash script from the top level directory. sed -i'' '30,${s/#define POST/#define POSTCODE/g;}' \ src/commonlib/include/commonlib/console/post_codes.h; myArray=`grep -e "^#define POSTCODE_" \ src/commonlib/include/commonlib/console/post_codes.h | \ grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2`; for str in ${myArray[@]}; do splitstr=`echo $str | cut -d '_' -f2-` grep -r POST_$splitstr src | \ cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"; grep -r "POST_$splitstr" util/cbfstool | \ cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"; done Change-Id: I25db79fa15f032c08678f66d86c10c928b7de9b8 Signed-off-by: lilacious <yuchenhe126@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/soc/intel/common/block')
-rw-r--r--src/soc/intel/common/block/cpu/car/cache_as_ram.S2
-rw-r--r--src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S4
-rw-r--r--src/soc/intel/common/block/graphics/graphics.c4
-rw-r--r--src/soc/intel/common/block/p2sb/p2sblib.c4
-rw-r--r--src/soc/intel/common/block/pmc/pmc.c2
5 files changed, 8 insertions, 8 deletions
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index f2ae72c38a..5f6b6de07c 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -302,7 +302,7 @@ before_carstage:
/* Never reached */
.halt_forever:
- post_code(POST_DEAD_CODE)
+ post_code(POSTCODE_DEAD_CODE)
hlt
jmp .halt_forever
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
index 0126a122f6..7532c7d707 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
@@ -20,7 +20,7 @@ bootblock_pre_c_entry:
.global cache_as_ram
cache_as_ram:
- post_code(POST_BOOTBLOCK_CAR)
+ post_code(POSTCODE_BOOTBLOCK_CAR)
movl $(CONFIG_FSP_T_LOCATION), %ebx
add $0x94, %ebx
@@ -99,7 +99,7 @@ CAR_init_done:
/* Never reached */
.halt_forever:
- post_code(POST_DEAD_CODE)
+ post_code(POSTCODE_DEAD_CODE)
hlt
jmp .halt_forever
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index 81a5d342f0..f163e229a9 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -117,7 +117,7 @@ uintptr_t graphics_get_framebuffer_address(void)
memory_base = graphics_get_bar(dev, PCI_BASE_ADDRESS_2);
if (!memory_base)
- die_with_post_code(POST_HW_INIT_FAILURE,
+ die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"Graphic memory bar2 is not programmed!");
memory_base += CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET;
@@ -140,7 +140,7 @@ static uintptr_t graphics_get_gtt_base(void)
if (!gtt_base) {
gtt_base = graphics_get_bar(dev, PCI_BASE_ADDRESS_0);
if (!gtt_base)
- die_with_post_code(POST_HW_INIT_FAILURE,
+ die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"GTTMMADR is not programmed!");
}
return gtt_base;
diff --git a/src/soc/intel/common/block/p2sb/p2sblib.c b/src/soc/intel/common/block/p2sb/p2sblib.c
index 537f388cb2..70fbcaa147 100644
--- a/src/soc/intel/common/block/p2sb/p2sblib.c
+++ b/src/soc/intel/common/block/p2sb/p2sblib.c
@@ -50,7 +50,7 @@ void p2sb_dev_unhide(pci_devfn_t dev)
p2sb_dev_set_hide_bit(dev, 0);
if (p2sb_dev_is_hidden(dev))
- die_with_post_code(POST_HW_INIT_FAILURE,
+ die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"Unable to unhide the P2SB device!\n");
}
@@ -59,7 +59,7 @@ void p2sb_dev_hide(pci_devfn_t dev)
p2sb_dev_set_hide_bit(dev, 1);
if (!p2sb_dev_is_hidden(dev))
- die_with_post_code(POST_HW_INIT_FAILURE,
+ die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"Unable to hide the P2SB device!\n");
}
diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c
index 37d857978c..2805011a78 100644
--- a/src/soc/intel/common/block/pmc/pmc.c
+++ b/src/soc/intel/common/block/pmc/pmc.c
@@ -62,7 +62,7 @@ static void pch_pmc_read_resources(struct device *dev)
struct pmc_resource_config *config = &pmc_cfg;
if (pmc_soc_get_resources(config) < 0)
- die_with_post_code(POST_HW_INIT_FAILURE,
+ die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"Unable to get PMC controller resource information!");
/* Get the normal PCI resources of this device. */