diff options
| author | Eran Mitrani <mitrani@google.com> | 2022-05-25 16:29:19 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-15 23:58:31 +0000 |
| commit | 400c30005e11e155a58f4acfc9bc5d4f34ece5a4 (patch) | |
| tree | 93aaac46e8634c4db7e01376a09d4bcde731626d /src/soc/intel/common/block | |
| parent | 14908bf05ad3cb5a44c1a0a8197f04e5cd8658d9 (diff) | |
soc/intel/common: support for configurable memory regions claimed by SA
see https://review.coreboot.org/c/coreboot/+/65072/8
BUG=b:149830546
BRANCH=firmware-brya-14505.B
TEST='emerge-brya coreboot chromeos-bootimage' builds correctly.
Tested on an Anahera device which successfully boots to ChromeOS
with kernel version 5.10.109-15688-g857e654d1705.
Change-Id: I80df95f9146934d6a2d23e525c22be3a9a7e2b9f
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64677
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block')
3 files changed, 39 insertions, 11 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h index 174c1a6d35..64e9be6bf9 100644 --- a/src/soc/intel/common/block/include/intelblocks/systemagent.h +++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h @@ -17,6 +17,23 @@ #define TSEG 0xb8 /* TSEG base */ #define TOLUD 0xbc /* Top of Low Used Memory */ +/* PCIEXBAR register fields */ +#define PCIEXBAR_LENGTH_4096MB 6 +#define PCIEXBAR_LENGTH_2048MB 5 +#define PCIEXBAR_LENGTH_1024MB 4 +#define PCIEXBAR_LENGTH_512MB 3 +#define PCIEXBAR_LENGTH_64MB 2 +#define PCIEXBAR_LENGTH_128MB 1 +#define PCIEXBAR_LENGTH_256MB 0 +#define PCIEXBAR_PCIEXBAREN (1 << 0) + +/* GMCH Graphics Control Register */ +#define GGC 0x50 +#define G_GMS_OFFSET 0x8 +#define G_GMS_MASK 0xff00 +#define G_GGMS_OFFSET 0x6 +#define G_GGMS_MASK 0xc0 + /* MCHBAR */ #define MCHBAR8(x) (*(volatile u8 *)(uintptr_t)(MCH_BASE_ADDRESS + x)) #define MCHBAR16(x) (*(volatile u16 *)(uintptr_t)(MCH_BASE_ADDRESS + x)) @@ -95,6 +112,13 @@ void soc_systemagent_init(struct device *dev); */ void soc_add_fixed_mmio_resources(struct device *dev, int *resource_cnt); +/* + * SoC call to provide all known configurable memory ranges for Device 0:0.0. + * SoC function should provide configurable resource ranges in form of + * struct sa_mmio_descriptor along with resource count. + */ +void soc_add_configurable_mmio_resources(struct device *dev, int *resource_cnt); + /* SoC specific APIs to get UNCORE PRMRR base and mask values * returns 0, if able to get base and mask values; otherwise returns -1 */ int soc_get_uncore_prmmr_base_and_mask(uint64_t *base, uint64_t *mask); diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 55e892c941..19a413f9d1 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -30,6 +30,12 @@ __weak void soc_add_fixed_mmio_resources(struct device *dev, /* no-op */ } +__weak void soc_add_configurable_mmio_resources(struct device *dev, + int *resource_cnt) +{ + /* no-op */ +} + __weak int soc_get_uncore_prmmr_base_and_mask(uint64_t *base, uint64_t *mask) { @@ -98,6 +104,10 @@ void sa_add_fixed_mmio_resources(struct device *dev, int *resource_cnt, size = sa_fixed_resources[i].size; base = sa_fixed_resources[i].base; + printk(BIOS_DEBUG, "SA MMIO resource: %s -> base = 0x%llx, size = 0x%llx\n", + sa_fixed_resources[i].description, sa_fixed_resources[i].base, + sa_fixed_resources[i].size); + mmio_resource(dev, index++, base / KiB, size / KiB); } @@ -273,6 +283,10 @@ static void systemagent_read_resources(struct device *dev) /* Add all fixed MMIO resources. */ soc_add_fixed_mmio_resources(dev, &index); + + /* Add all configurable MMIO resources. */ + soc_add_configurable_mmio_resources(dev, &index); + /* Calculate and add DRAM resources. */ sa_add_dram_resources(dev, &index); if (CONFIG(SA_ENABLE_IMR)) diff --git a/src/soc/intel/common/block/systemagent/systemagent_def.h b/src/soc/intel/common/block/systemagent/systemagent_def.h index 0add13e93e..09a99ea2e9 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_def.h +++ b/src/soc/intel/common/block/systemagent/systemagent_def.h @@ -5,12 +5,7 @@ /* Device 0:0.0 PCI configuration space */ -/* GMCH Graphics Control Register */ -#define GGC 0x50 -#define G_GMS_OFFSET 0x8 -#define G_GMS_MASK 0xff00 -#define G_GGMS_OFFSET 0x6 -#define G_GGMS_MASK 0xc0 + /* DPR register in case CONFIG_SA_ENABLE_DPR is selected by SoC */ #define DPR 0x5c #define DPR_EPM (1 << 2) @@ -22,11 +17,6 @@ #define CAPID_PDCD (1 << 12) #define CAPID_DDRSZ(x) (((x) >> 19) & 0x3) -#define PCIEXBAR_LENGTH_64MB 2 -#define PCIEXBAR_LENGTH_128MB 1 -#define PCIEXBAR_LENGTH_256MB 0 -#define PCIEXBAR_PCIEXBAREN (1 << 0) - #define PAM0 0x80 #define PAM1 0x81 #define PAM2 0x82 |